Abstract:A reconfigurable radix-r FFT structure design is proposed, to reduce the memory and time consumption caused by zero-paddling in traditional radix-2/4 methods. The radix-r FFT computing flow is divided into three iterative steps: rotate factors computation; memory access schedule; butterfly coefficients matrix multiplication. The hardware structure is depicted, in which the memory accessing schedule is implemented by a finite state machine, the rotate factors and butterfly coefficients are calculated by the Tay… Show more
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