A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier

Abstract

This paper describes an efficient technique for the design of fault-secure VLSI circuits based on differential cascode voltage switch (DCVS) logic. We propose a new synthesis method for constructing DCVS circuits with a near-optimal transistor count based on binary decision diagrams (BDDs). The time and memory resources required are very low, making the technique practical even for PC-based synthesis tools. This method is the basis for a CAD tool that allows automatic synthesis of fault-secure circuits based on the DCVS technology. We finally present an improved design and implementation of a 2's complement serial/parallel multiplier as an application of the proposed technique and algorithm.

Synthesize pass transistor logic gate by using free binary decision diagram

“…[4], SRPL (Swing Restored Pass transistor Logic) [ 5 ] , CPL (Complimentary Pass transistor Logic) [7], or SPL (Single rail Pass transistor Logic) [6]), take attention because of low power consumption and high speed switching characteristic.…”