A new edge-defined approach for submicrometer MOSFET fabrication

Abstract

A novel technique emploging vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described, and preliminary results are presented. Three basic process techniques are employed: formation of En edge-defined submicrometer element, pattern transfer of the element into an underlying doped polysilicon gate layer, and passivation of the FET using a sidewall oxide. The submicrometer element formation technique is limited to linewidths in the 0.1 pm to 0.4 pm range. Characterization of MOSFETs, having physical channel lengths -0.1 pm to 0.15 pm and believed to be the world's smallest MOSFET's reported to date, is discussed. M any methods have been used to fabricate submicrometer MOSFETs or MESFETs, including overetching of optically defined patterns [l], submicrometer lithography using electron-beam [2j and X-rays 131, diffusion techniques using double diffusion (DMOS) [4] or V-grooves (VMOS) [5], and edge-defined processing [6], [7].In the latter category of edge-defined processing, two techniques have previously been discussed in the literature. Ipri[6] has employed the method developed by Nicholas, et al. [8]~ of forming p+ polysilicon gates, using the selective removal of non-p+ doped polysilicon, in CMOS/SOS processing, while Jackson et al. [7] have used edge plating of Au over Cr and other metals to fabricate GaAs MESFETs. A novel technique employing vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described and preliminary results are presented. PROCESS APPROACHES Three basic fabrication techniques are employed: formation of an edge-defined submicrometer element (Figures la, b), pattern transfer of the element into a doped polysilicon gate layer (Figure IC), and the passivation of the transistor using a sidewall oxide (Figure Id). A pattern having a vertical step in an oxide layer (the top layer of an oxide/nitride/n+ doped, polysiliconlgate oxide/substrate-silicon stack) is formed using a fluorocarbon-based anisotropic dry etch in a parallel-plate reactor (Figure la). This step is then conformally coated by a low-pressure CVD deposition of undoped polysilicon which results in a thickness of polysilicon at the step (normal to the slice) greater than the thickness in regions far removed from the step. A controlled anisotropic overetch of the polysilicon in the distant regions results in a subThe authors are with Central Research Laboratories, Texas Instruments 1980. Incorporated, Dallas, Texas 75265.micrometer element of polysilicon left at the step. Removal of the oxide template using an HF containing etch results in the completion of the free-standing submicrometer element (Figure lb).Fig. 1. Process sequence showing cross-section: (a) after anisotropic etching of oxide template layer, (b) after forming submicrometer polysilicon elements, (c) after transfer into underlying polysilicon gate layer, and (d) after sidewall oxide formation.The submicrometer element width, which determines the FET channel length, is itself determined by the thic...

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