A new device interconnect scheme for sub-micron VLSI

Abstract

A new device interconnect scheme for sub-micron VLSI has been developed. In this technology N+ and P+ diffusions and N+ and P+ gates of a CMOS process can be directly connected in any combination desired without the use of contacts or aluminum. This provides much improved packing density over conventional processes. Since the source/drain (S/D) contacts can extend over the field oxide regions, minimum sized S/D diffusion areas can be used. This leads to a significant decrease in parasitic diffusion capacitances relative to other processes. Several. devices can share one contact when they need to communicate, and so the total number of contacts can be greatly reduced. Since the contacts do not have to be limited to minimum dimensions a relaxation of sub-micron contact processing is achieved. In addition the use of a self-aligned silicide reduces interconnect and other device parasitic resistances. NMOS and PMOS devices have been successfully fabricated using this process.

Silicides and local interconnections for high-performance VLSI applications

“…The process flows for each are detailed in Figures 19-22. The silicide-based ( Figure 19) and TiN-based local interconnection (Figure 20) approaches are similar in that the silicide contacts to the source, gate, and drain regions and the local interconnections between those regions are formed simultaneously during thermal processing [4]. The selective CVD tungsten-based local interconnection approach detailed in Figure 21 is similar to the silicidebased and TiN-based local interconnection approaches in that the source, gate, and drain contacts and the local interconnections are all formed concurrently.…”

“…Several schemes have been proposed over the last ten years for forming an additional level of interconnection for localized wiring purposes [4][5][6][7][8][9][10][11]. Because the local interconnection schemes require only one additional masking level and generally provide a 20-30% improvement in SRAM cell size, the productivity improvement is clear for SRAM and logic chips (e.g., microprocessor chips) requiring large amounts of on-chip cache.…”

“…Local interconnection approaches involving one additional mask level such as HPSAC (high-performance silicided amorphous-silicon contact and interconnection technology) [4] and the use of a patterned TiN layer [5] were first proposed in 1985. Since then, several other modifications and promising approaches have been developed [6][7][8][9][10][11].…”