A new CR-delay circuit technology for high-density and high-speed DRAMs

On-chip High-Voltage Generator Design

“…The capacitor voltages V CAP1,2 increase linearly to time with I REF .After the source voltages of M2,3 reach V R , the impedance of M2,3 rapidly increases, resulting in rapid increase in the drain voltages of M2,3. The delay time from the time when V CAP1 starts going up to the time when V CAP1 reaches V R is given by 14 Delay circuit with a delay time proportional to CR(Watanabe et al 1989) CV R /I REF . Even though V R and I REF vary according to the threshold voltage of M1, their ratio is constant as R as given below.…”