A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes

Sogomonyan, E.S.; Ocheretnij, V.; Gössel, Michael

doi:10.1109/ats.2001.990310

Cited by 16 publications

(14 citation statements)

References 4 publications

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“…In the previously proposed fault-secure adders [9], [11], all the carry (or sum) bits are compared with the corresponding redundant ones. Because only one half of the carry bits are compared in our adder, the two-rail checker and wiring area are smaller.…”

Section: Low-overhead Fault-secure Parallel Prefix Addermentioning

confidence: 99%

“…Although a ripple carry adder is basic and simple, it is too slow for many applications. In [9] and [10], a fault-secure and self-testing carry lookahead adder and a fault-secure and self-testing carry skip adder are shown, respectively. A circuit is said to be self-testing, if, for any fault, at least one input pattern exists to detect the fault.…”

Section: Introductionmentioning

confidence: 99%

“…In this adder, all the carry bits are compared with the corresponding redundant carry bits for checking. In the previously proposed adders using carry-bit (or sum-bit) duplication [9]- [11], all the carry bits (or sum bits) are compared with the corresponding redundant bits for checking. On the other hand, in the adder proposed in this paper, only one half of the carry bits are compared.…”

Section: Introductionmentioning

confidence: 99%

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Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Kito

Takagi

2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predict the parity of the result. The adder uses paritybased error detection and it has high compatibility with systems that have parity-based error detection. We can implement various fault-secure parallel prefix adders such as Sklansky adder, Brent-Kung adder, Han-Carlson adder, and Kogge-Stone adder. The area overhead of the proposed adder is about 15% lower than that of a previously proposed adder that compares all the carry bits. key words: parity prediction, parallel prefix adder, fault secure, carry-bit duplication

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Section: Low-overhead Fault-secure Parallel Prefix Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Kito

Takagi

2013

IEICE Trans. Inf. & Syst.

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“…Since fault occurrence in the current CMOS systems is extremely rare, existing fault tolerance schemes for adders can typically afford to utilize coding based approaches or fault masking approaches [11,12]. Related previous work also includes online detection of faults in adders [13,14,15,16,17]; yet online identification of the faulty locations has not been tackled in CMOS adders.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, parallel adders, providing an optimal performance with C12 [8,11] C8 [4,7] [0, 3] [12,15] Figure 1: Hierarchical implementation of a 64-bit CLA but also support efficient online repair based fault tolerance. Since a CLA is constructed with regular blocks with inputs disjoint across the blocks, precise component-level fault identification within the adder can be approached with low hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics

Rao

Orailoğlu

Karri³

Eleventh IEEE European Test Symposium (ETS'06)

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Online repair through reconfiguration is a particularly advantageous approach in the nanoelectronic environment since reconfigurability is naturally supported by the devices. However, precise identification of faulty locations is of critical importance for fine-grain repairs.A CLA is mainly composed of: (1) carry generation blocks and (2) g,p signal generation blocks. In this paper we propose two schemes for fault identification in these two parts correspondingly. For carry generation blocks, an inherently redundant computation path is exploited to identify the faulty block with high precision. As a time redundancy approach, recomputation with rotated operands (RERO) has been utilized in online fault detection for CLA's [13]. For g,p generation blocks, we exploit the RERO scheme to achieve precise fault identification.A comprehensive analysis is provided for the aliasing in the proposed fault identification approach. It is shown that both the amount of repair hardware overhead and the fault coverage loss for the proposed scheme are very low. Overall, the proposed scheme can perform fast and precise identification of faults in the CLA components with low area overhead, thus facilitating the development of powerful and efficient fault tolerance schemes through online repair for nanoelectronic systems.

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New Methods of Concurrent Checking

Sogomonyan¹

2008

Frontiers in Electronic Testing

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A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes

Cited by 16 publications

References 4 publications

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics

New Methods of Concurrent Checking

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