where rSub ϭ rSub Ј Ϫ j rSub Љ and Sub ϭ 1/ Sub are the equivalent relative permittivity and equivalent conductivity of the multilayer substrate formed by the silicon and the silicon dioxide. With these realistic parameter values, the agreement between measurements and simulations is very good, even for the phase of S 21 given in Figure 4(b).
DISCUSSIONThe insertion losses have to be reduced so that this kind of filter can be integrated into front-ends for a few GHz operating frequencies. We have studied the origin of the filter insertion losses. They can be divided into three contributions: the CPW transmission line metallic losses, the varactors series resistance, and the silicon losses.The reduction of the CPW transmission line metallic losses could be carried out by enlarging the CPW central conductor width W 0 , and consequently the gap width G 0 , to keep the same characteristic impedance of the unloaded transmission line. Nevertheless, enlarging the gap width induces a greater penetration of electric field in the silicon substrate, thus potentially enlarging dielectric losses. Then the use of a high-resistivity silicon (HR Si) substrate or SOI substrate could allow minimizing the contribution of substrate losses. Finally, the varactors must be inserted inside the CPW gap so that the series resistance can be minimized.Considering the parameters given in Table 1 and a 465 fFcapacitance value C vmean of the varactors leading to filter mean cutoff frequency of 4.3 GHz, the contribution of each insertion losses source has been studied. Figure 5 shows that improved filter behaviors could be obtained considering the realistic parameters values listed as follows:The series resistance R s given by the manufacturer fixed to 2 ⍀ instead of 10 ⍀. In practice, this value could be obtained if the varactors were designed inside the CPW gap. A low-loss substrate corresponding to HR Si or SOI substrate ( Si ϭ 4000 ⍀ cm instead of 110 ⍀ cm). An enlarged CPW design to reduce conductor losses (W 0 ϭ 10 m and G 0 ϭ 95 m instead of W 0 ϭ 3 m and G 0 ϭ 34.5 m).These simulations show that considering a 2-⍀ series resistance compared with the actual manufactured filter allows to decrease the insertion loss by about 1.4 dB at 4.3 GHz ( S 21 ϭ Ϫ5.7 dB instead of Ϫ7.3 dB). If we consider this 2-⍀ series resistance on a HR Si ( Si ϭ 4000 ⍀ cm), the insertion loss at 4.3 GHz is S 21 ϭ Ϫ4.8 dB. Finally, by enlarging the CPW design on a HR Si, with varactors inserted inside the CPW gap (R s ϭ 2 ⍀), the insertion loss could be reduced by ϳ2.5 dB in the passband, leading to S 21 ϭ Ϫ2.3 dB at 4.3 GHz.
CONCLUSIONA compact coplanar tunable low-pass filter, integrated on a lowresistivity standard silicon substrate, has been presented in this article. The performances of the filter are very interesting when compared with its ultra compact size. A Ϯ19% cutoff-frequency tuning around 4.3 GHz without any spurious peak until 30 GHz has been obtained. Insertion losses are mainly due to the conductor at low frequencies (1.5 dB). As explained earlier,...