“…Work on gate and device sizing (the main topics of this paper) can be found in, e.g., Chu and Wong (2001b), Passy (1998), Cong and He (1999), Kasamsetty et al (2000), Matson and Glasser (1986), Pattanaik et al (2003), Shyu et al (1988), Sancheti and Sapatnekar (1996), Sapatnekar and Chuang (2000), and Sapatnekar et al (1993). These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models. Work on interconnect sizing (also addressed in this paper) includes Alpert et al (2001b), , Cong and Koh (1994), , Cong and Leung (1995), Cong and Pan (2002), Chen et al (2004), , Gao and Wong (1999), Kay and Pileggi (1998), Lee et al (2002), Lin and Pileggi (2001), and Sapatnekar (1996); simultaneous gate and wire sizing is considered in and Jiang et al (2000).…”