A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]

The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multiobjective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.

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“…If solution is satisfying the problem is solved, otherwise the decision maker will ask for another aspiration level [7][8].…”

Section: Satisficing Trade-off Methods (Stom)mentioning

confidence: 99%

“…We used posynomial functions for modeling circuit the power and delay values. These functions are convex when the variables have positive value [7]. Again the model is obtained by interpolation of the sampling points, and finding the best fitting coefficients.…”

Section: Definition (1): a Functionmentioning

confidence: 99%

Multi-objective optimization techniques for VLSI circuits

Kashfi

Hatami

Pedram

2011

2011 12th International Symposium on Quality Electronic Design

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“…Since then many digital circuit design problems have been formulated as GPs or related problems. Work on gate and device sizing (the main topics of this paper) can be found in, e.g., Chu and Wong (2001b), Passy (1998), Cong and He (1999), Kasamsetty et al (2000), Matson and Glasser (1986), Pattanaik et al (2003), Shyu et al (1988), Sancheti and Sapatnekar (1996), Sapatnekar and Chuang (2000), and Sapatnekar et al (1993). These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models.…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

“…Work on gate and device sizing (the main topics of this paper) can be found in, e.g., Chu and Wong (2001b), Passy (1998), Cong and He (1999), Kasamsetty et al (2000), Matson and Glasser (1986), Pattanaik et al (2003), Shyu et al (1988), Sancheti and Sapatnekar (1996), Sapatnekar and Chuang (2000), and Sapatnekar et al (1993). These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models. Work on interconnect sizing (also addressed in this paper) includes Alpert et al (2001b), , Cong and Koh (1994), , Cong and Leung (1995), Cong and Pan (2002), Chen et al (2004), , Gao and Wong (1999), Kay and Pileggi (1998), Lee et al (2002), Lin and Pileggi (2001), and Sapatnekar (1996); simultaneous gate and wire sizing is considered in and Jiang et al (2000).…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

“…The influential book by Sutherland et al (1999) is almost entirely devoted to the sizing problem. Sizing of digital circuits is a wellresearched field, with hundreds of papers on the topic; see, e.g., the articles by Fishburn and Dunlop (1985), Passy (1998), Chen et al (2004), Kim et al (2004), Kasamsetty et al (2000), Sapatnekar (1996), and Sapatnekar et al (1993) and the references therein.…”

Section: Digital Circuit Sizingmentioning

confidence: 99%

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Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Convex Optimization

Sapatnekar

2007

Wiley Encyclopedia of Computer Science and Engineering

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Several practical problems in computer science and computer engineering may be framed as convex optimization problems. Unlike a general optimization formulation that may be trapped in a local minimum, necessitating hill‐climbing methods to crawl out of such a minimum, a convex optimization formulation has the attractive property that any local minimum is guaranteed to be a global minimum. This chapter presents an overview of the theory behind convex optimization and some illustrative examples of representative problems that are convex programs.

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A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]

Cited by 66 publications

References 8 publications

Multi-objective optimization techniques for VLSI circuits

Multi-objective optimization techniques for VLSI circuits

Digital Circuit Optimization via Geometric Programming

Convex Optimization

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