A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

Farkhani, Hooman; Peiravi, Ali; Moradi, Farshad

doi:10.1016/j.mejo.2014.09.006

Cited by 25 publications

(20 citation statements)

References 25 publications

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“…Though this approach suffers from enhanced write/read access time. Also, with scaling in supply voltage in presence of process variations, write and read sensing capacity further reduces in single-ended methodologies [4,6,7,20,21]. This may be owed to absence of complimentary bit-line.…”

Section: State Of the Artmentioning

confidence: 99%

“…This may be owed to absence of complimentary bit-line. To eradicate this issue a few Singleended write and read topologies were proposed with various assist techniques [4,6,20]. Though, for implementing these assists, silicon area is necessitated that is considered to be substantial trade-off as seen in current demand for higher memories and reduced device sizes.…”

Section: State Of the Artmentioning

confidence: 99%

“…Besides, many methodologies have been reviewed for curtailing power dissipation along with enhancement in access time and stability while keeping other parameters in control. This include read assist circuit [4], decoupling of read and write ports [5], write assist circuit [6], and loop-cutting approach [7] for simultaneous improvement in read and write noise margins along with voltage scaling. M. Ansari et al [8] proposed a 7T SRAM cell to enhance read static noise margin (RSNM) of bit cell at lower supply voltage.…”

Section: State Of the Artmentioning

confidence: 99%

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Design of 10T SRAM cell with improved read performance and expanded write margin

Sachdeva

Tomar

2020

IET Circuits, Devices & Syst

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The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

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Section: State Of the Artmentioning

confidence: 99%

Section: State Of the Artmentioning

confidence: 99%

Section: State Of the Artmentioning

confidence: 99%

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Design of 10T SRAM cell with improved read performance and expanded write margin

Sachdeva

Tomar

2020

IET Circuits, Devices & Syst

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“…On the other hand, power consumption of the system is decreasing (Ahmad et al , 2019; Birla, 2019). Due to the property of quadratic reduction in power, the scaling of the supply voltage is very essential (Farkhani et al , 2014). This entails near-threshold and subthreshold, which strive to attain the minimum energy point.…”

Section: Introductionmentioning

confidence: 99%

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Mishra

Vaithiyanathan

Pal

et al. 2021

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Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

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“…At the architec-ture level, proposed read and write assist techniques in literature can improve SRAM robustness and performance while occupying less area compared to the cell techniques (e.g. 8T and 10T) and can be used with any type of SRAM [16,17]. To understand the existing challenges in SRAM design let us explain the operation of standard 6T-SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology

Moradi

Tohidi

Zeinali

et al. 2015

VLSI-SoC: Internet of Things Foundations

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SRAM operation at subthreshold/weak inversion region provides a significant power reduction for digital circuits. SRAM arrays which contribute to a large amount of power consumption for the processors in sub-100nm technologies, however, cannot benefit from subthreshold operation. To this end, new SRAM technique on the circuit or architecture level is required. In this chapter, a novel 8T-SRAM cell is proposed which shows a significant improvement in write margin by at least 22% in comparison to the standard 6T-SRAM cell at supply voltage of 1V. Furthermore, read static noise margin of the proposed cell is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for superthreshold region, the proposed cell is able to work at supply voltages lower than 200mV through which the total power consumption and the robustness of the cell are improved significantly. The proposed circuit is designed in 65nm CMOS TSMC technology.

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A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

Cited by 25 publications

References 25 publications

Design of 10T SRAM cell with improved read performance and expanded write margin

Design of 10T SRAM cell with improved read performance and expanded write margin

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology

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