A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)

Rybalkin, Vladimir; Schläfer, Philipp; Wehn, Norbert

doi:10.1109/vtcspring.2016.7504085

Cited by 7 publications

(10 citation statements)

References 14 publications

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“…In [59], finite-length NB protographbased (NBPB) LDPC codes are proposed, which choose the edge weights and show coding gains in about 256 bits of code length. In [60], NB-LDPC codes in a field of GF(256) have a parallel decoding structure and greatly reduce decoding latency. As rateless codes, LT codes and Raptor codes [61] show flexibility in error controlling capability and are used in multimedia dissemination.…”

Section: ) Advances Of Codes For Hrll Communicationsmentioning

confidence: 99%

High-Reliability and Low-Latency Wireless Communication for Internet of Things: Challenges, Fundamentals, and Enabling Technologies

Xiao

et al. 2019

IEEE Internet Things J.

213

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As one of the key enabling technologies of emerging smart societies and industries (i.e., industry 4.0), the Internet of Things (IoT) has evolved significantly in both technologies and applications. It is estimated that more than 25 billion devices will be connected by wireless IoT networks by 2020. In addition to ubiquitous connectivity, many envisioned applications of IoT, such as industrial automation, vehicle-to-everything (V2X) networks, smart grids and remote surgery, will have stringent transmission latency and reliability requirements, which may not be supported by existing systems. Thus, there is an urgent need for rethinking the entire communication protocol stack for wireless IoT networks. In this tutorial paper, we review the various application scenarios, fundamental performance limits, and potential technical solutions for high-reliability and lowlatency (HRLL) wireless IoT networks. We discuss physical, MAC and network layers of wireless IoT networks, which all have significant impacts on latency and reliability. For the physical layer, we discuss the fundamental information-theoretic limits for HRLL communications, and then we also introduce a frame structure and preamble design for HRLL communications. Then practical channel codes with finite block length are reviewed. For the MAC layer, we first discuss optimized spectrum and power resource management schemes and then recently proposed grantfree schemes are discussed. For the network layer, we discuss the optimized network structure (traffic dispersion and network densification), the optimal traffic allocation schemes and network coding schemes to minimize latency.

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Section: ) Advances Of Codes For Hrll Communicationsmentioning

confidence: 99%

High-Reliability and Low-Latency Wireless Communication for Internet of Things: Challenges, Fundamentals, and Enabling Technologies

Xiao

et al. 2019

IEEE Internet Things J.

213

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“…Thus, removing the RE process from the ECN processing avoids performance degradation. Let us define a modified ECN operation with symbol ⊞ ′ where the ECN addition is performed as in (12) and no RE is performed. The syndrome set of size n m can then be computed as…”

Section: A Syndrome Computation Using the Ef Processingmentioning

confidence: 99%

“…The throughput of a layered decoder is given by T = (N b × F clk × p)/(M × CL(layer) × it avr ) where it avr is the average number of iterations and F clk is fixed at 800 MHz. The layered GF(64) (1536, 1344) code allows different parallelism options depending on the splitting factor [28] (p = 2, 3,4,6,8,12,16,24,32,48,96). With an observed average number of iterations at SNR = 4.0 of 1.5 and a parallelism of 12, the throughput can reach 1.2 Gbps with p = 2 and 7.3 Gbps with p = 12.…”

Section: E Throughputmentioning

confidence: 99%

“…The SB algorithm, recently presented in [10] [11], is an efficient method to perform a parallel computation of the CN when q ≥ 16. This architecture was used for the first reported implementation of a GF(256) CN processor with degree d c = 4 [12]. However, the complexity of the SB CN algorithm is dominated by the number of syndromes to be computed, which increases quadratically with d c , limiting its interest for high coding rates, i.e.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid Check Node Architectures for NB-LDPC Decoders

Marchand

Boutillon

Harb

et al. 2019

IEEE Trans. Circuits Syst. I

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This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.

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“…Although NB-LDPC codes provide a better error rate performance compared to binary LDPC codes, the high computation and storage complexity required by high-order NB-LDPC decoders limits its practical usage [13]. In order to reduce the complexity of the decoder, the extended Min-Sum (EMS) algorithm [14]- [16], the Min-Max algorithm [17]- [20] and a syndrome-based check node (SYN CN) algorithm [21] [22] are proposed. It was demonstrated in [23] that, compared to the Min-Max algorithm, the EMS algorithm is able to achieve a better error-rate performance and, hence, is considered in this paper.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Short High-Order Non-Binary LDPC Decoder Architecture Using a Message-Adaptation EMS Algorithm

Chu

Lee

et al. 2021

IEEE Access

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Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm 2 . The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.INDEX TERMS Non-binary low-density parity-check (NB-LDPC) codes, message-adaptation extended min-sum (MA-EMS) algorithm, layered decoding, early termination (ET), very large scale integration (VLSI) architecture.

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A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)

Cited by 7 publications

References 14 publications

High-Reliability and Low-Latency Wireless Communication for Internet of Things: Challenges, Fundamentals, and Enabling Technologies

High-Reliability and Low-Latency Wireless Communication for Internet of Things: Challenges, Fundamentals, and Enabling Technologies

Hybrid Check Node Architectures for NB-LDPC Decoders

An Efficient Short High-Order Non-Binary LDPC Decoder Architecture Using a Message-Adaptation EMS Algorithm

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