A new approach to thermometer-to-binary encoder of flash ADCs- bubble error detection circuit

Hieu, Bui Van; Choi, Seung-Hwan; Seon, Jong-Kug; Oh, Young-Cheol; Park, Chongdae; Park, Jaehyoun; Kim, Hyun‐Wook; Jeong, Taikyeong

doi:10.1109/mwscas.2011.6026403

Cited by 22 publications

(4 citation statements)

References 15 publications

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“…There are: Fat-tree encoder [15]; MUX-based encoder [16,17]; bubble error correction (BEC) circuit [18]; ROM based encoder [19]; logic-based encoder [20]. All the methods are proposing the same advantages such as high speed, high resolution, low power etc.…”

Section: Grey Code Circuitsmentioning

confidence: 99%

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A low power serial output flash ADC in 0,18 µm CMOS process

Reaz

Amin

et al. 2015

Teh. vjesn.

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Original scientific paper This paper proposes a simple design of a flash analog-to-digital converter (ADC) in 0,18 μm CMOS technology. This ADC is expected to be used within a temperature sensor, which provides analog data output having a range of 360 mV to 560 mV. This system consists of three main blocks: the threshold inverter quantization (TIQ)-comparator, encoder and parallel input serial output (PISO) register. The design goal is to get a flash ADC with low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length, for finding out the threshold voltage difference of the inverter each on the TIQ comparator. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844,48 × 764,77 µm 2 and the power dissipation is 0,162 µW with 1,6 V supply voltage. Keywords: CMOS, Comparator, Flash ADC, Temperature Sensor Serijski izlazni impulsni ADC male snage u 0,18 µm CMOS postupkuIzvorni znanstveni članak U radu se predlaže jednostavan projekt impulsno analogno-digitalnog pretvarača (ADC) u 0,18 μm CMOS tehnologiji. Taj bi se pretvarač trebao koristiti u senzoru temperature, koji daje izlaz analognih podataka u rasponu od 360 mV do 560 mV. Sustav se sastoji od tri glavna bloka: threshold inverter quantization (TIQ) -komparatora, kodnog uređaja (kodera) i parallel input serial output (PISO) registra. Svrha je projekta dobiti impulsni ADC s malim gubitkom energije, malih dimenzija i kompatibilnim sa senzorima temperature. Ovom bi se metodom trebala podesiti dužina svakog kanala tranzistora u svrhu pronalaženja razlike u ulaznom naponu pretvarača na TIQ komparatoru. Projektom se predviđa ulazni raspon od 285 do 600 mV i izlaz rezolucije 6-bita. Površina čipa projektiranog ADC je 844,48 × 764,77 µm 2 a gubitak energije iznosi 0,162 µW uz napajanje od 1,6 V.

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Section: Grey Code Circuitsmentioning

confidence: 99%

“…The bubble error is the result of many sources, for instance, clock jitter, device mismatch, offset voltage. The input thermometer code of a circuit is invalid code and there is no correction circuit, consequently output of the ADC in this case is incorrect [18].…”

Section: Grey Code Circuitsmentioning

confidence: 99%

A low power serial output flash ADC in 0,18 µm CMOS process

Reaz

Amin

et al. 2015

Teh. vjesn.

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“…Rest of the paper is organised as follows. In Section 2, comparison with three BECs, OR gate based BEC [3], AND gate based BEC [6, 7, 14, 19] and the proposed BEC for power and delay is presented. The complete encoder block using three different encoders namely Fat‐Tree encoder, modified Fat‐Tree encoder and MUX based encoder is studied in Section 3.…”

Section: Introductionmentioning

confidence: 99%

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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“…To prevent large errors due to bubbles in the thermometer code [9,15], the most effective procedure is to use a Wallace tree encoder [14,18]. Concerning the analog sector, in addition to designing the comparators with larger transistors, recently proposed approaches use redundancy, i.e., more comparators than necessary, but smaller, having an increased V OS .…”

Section: Introductionmentioning

confidence: 99%

A Flash ADC Tolerant to High Offset Voltage Comparators

Couto-Pinto

Fernandes

Piedade

et al. 2016

Circuits Syst Signal Process

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A conventional flash analog-to-digital converter (ADC) with a Wallace tree encoder ensures monotonicity and avoids missing codes, but still requires comparators with low offset voltage, which implies high area and power consumption. In this paper, we extend the purpose of this flash implementation, to allow the comparators to have extremely high offset voltages. This leads to a new approach toward the design of a flash ADC that does not require any type of calibration, allow easy porting among technologies and benefits from scaling. A statistical study is presented to demonstrate the effectiveness of the new method, and a modification is proposed to ensure fullrange operation. It is shown that a proposed N -bit ADC has a performance equivalent to an (N − m)-bit conventional flash ADC, with considerable gains in area and power consumption, with less design effort. The design flow of the OST ADC, with the necessary steps, is presented. A circuit, employing minimum dimension transistors, was fabricated in 0.13-µm CMOS and used as a proof of concept for the ADCs proposed here.

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A new approach to thermometer-to-binary encoder of flash ADCs- bubble error detection circuit

Cited by 22 publications

References 15 publications

A low power serial output flash ADC in 0,18 µm CMOS process

A low power serial output flash ADC in 0,18 µm CMOS process

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

A Flash ADC Tolerant to High Offset Voltage Comparators

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