A new algorithm to compute the DCT and its inverse

Li, W.

doi:10.1109/78.136537

Cited by 61 publications

(11 citation statements)

References 14 publications

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“…These equations can be presented in matrix form which is explained in [11] and these can be implemented in VLSI. Only a 16 words ROM is required as DCT components are separated into odd and even.…”

Section: Skew Circular Convolution Basedmentioning

confidence: 99%

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays

Khawam

Baloch

Pai

et al. 2004

Proceedings Design Automation and Test in Europe Conference and Exhibition DATE-04

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Mobile video processing as defined in standards like contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific reconfigurable arrays that have demonstrated up to 75% reduction in power consumption when compared to generic FPGA architecture, which makes them suitable for portable devices. This paper presents and compares different configurations of the arrays to efficiently implementing DCT and motion estimation algorithms. A number of algorithms are mapped into the various reconfigurable fabrics demonstrating the flexibility of the new reconfigurable SoC architecture and its ability to support a number of implementations having different performance characteristics

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Section: Skew Circular Convolution Basedmentioning

confidence: 99%

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays

Khawam

Baloch

Pai

et al. 2004

Proceedings Design Automation and Test in Europe Conference and Exhibition DATE-04

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show abstract

“…In order to realize DCT efficiently, many fast algorithms [5][6][7] are presented to reduce the computational complexity. Basically, there are two approaches for DCT implementation.…”

Section: Introductionmentioning

confidence: 99%

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

Hsia

Tsai

Wang

et al. 2009

J Sign Process Syst Sign Image Video Technol

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This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8×8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm 2 using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3~1/5 of the conventional DCT chips.

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“…They resemble Karhunen-Loeve transform for first-order Markov stationary random data and are classified into four groups [1]. Finding fast computational algorithms for DCTs has been a rather active subject [2,3,4,5,6]. These methods all tried to reduce the amount of multiplications.…”

Section: Introductionmentioning

confidence: 99%

Fast DCT-I, DCT-III, and DCT-IV via Moments

Liu

Wang

2005

EURASIP J. Adv. Signal Process.

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This paper presents a novel approach to compute DCT-I, DCT-III, and DCT-IV. By using a modular mapping and truncating, DCTs are approximated by linear sums of discrete moments computed fast only through additions. This enables us to use computational techniques developed for computing moments to compute DCTs efficiently. We demonstrate this by applying our earlier systolic solution to this problem. The method can also be applied to multidimensional DCTs as well as their inverses.

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A new algorithm to compute the DCT and its inverse

Cited by 61 publications

References 14 publications

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays

Efficient implementations of mobile video computations on domain-specific reconfigurable arrays

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

Fast DCT-I, DCT-III, and DCT-IV via Moments

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