A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model

Jiang, Dong; Wang, Xiangrui; Huang, Zhanhong; Yang, Yongkui; Yao, Enyi

doi:10.1109/tcsi.2023.3263923

Cited by 4 publications

(3 citation statements)

References 42 publications

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“…In the actual machine, the accuracy was reduced due to defects in some circuits, but accuracy in the 99th percentile was obtained for all benchmarks. Other work [9] computed with parallel spin updates and had comparable solution accuracies. Therefore, in the future, we would like to consider parallelizing the computation using an annealing method with parallel updates, which is suitable for the proposed system.…”

Section: Table 4 Theoretical and Actual Benchmark Results Of The Prop...mentioning

confidence: 99%

“…In the field of analog circuits, Oscillator Ising Machines [6] and bistable latch-based Ising machines [7] have been proposed, but both are sparselycoupled. In the field of digital circuits, FPGAs have been verified in various ways, including simulated bifurcation machines [8] and Network-on-Chip-based annealing processing [9]. In ASICs, several sparsely-coupled implementations have been proposed [10][11] and 1.3 M spins [12] have been achieved using 40 nm CMOS.…”

Section: B Related Workmentioning

confidence: 99%

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Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI

Megumi,

Endo,

Kawahara

2024

IEEE Access

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Annealing processors specialized for combinatorial optimization problems are attracting attention. Although a general-purpose fully-coupled type is required for annealing processors in CMOS, the complexity of the coupling has led to scalability issues. Therefore, a scalable structure has been proposed that divides the calculation into multiple chips and has already been verified by using FPGAs. In the proposed system, 4,096 spins are implemented on a single board by 36 22-nm CMOS LSIs (512-spin fully-coupled annealing processor) and 1 FPGA for control. This is the largest fully-coupled annealing processing system implemented on a single board. This paper describes two main techniques used in the proposed system. The first is an approximate halving of the number of chips (from 64 to 36) by reducing the interaction matrix, and the second is an 8-parallel-solution search by parallel operation after reducing the number of chips. We found that a single LSI and a control FPGA can operate as a 512-spin fully-coupled annealing processor. Compared with CPU, the proposed system with 36 LSIs and control FPGAs improves computation speed by a factor of 34.0 and power performance by a factor of 2,344, while searching for 8 solutions in parallel.

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Section: Table 4 Theoretical and Actual Benchmark Results Of The Prop...mentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI

Megumi,

Endo,

Kawahara

2024

IEEE Access

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show abstract

“…The architecture is scalable and modular in design. It can be used to create a massive tree in which several nodes can communicate with each other through their parents and root nodes [18]. The upcoming study may focus on network security techniques and their integration with NoC configurations for big clusters [19].…”

Section: Related Workmentioning

confidence: 99%

2D router chip design, analysis, and simulation for effective communication

Agarwal

Garg

Kumar

2023

IJ-ICT

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<p class="Correspondencedetails"><span lang="EN-US">The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.</span></p>

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A Genuine-Equilibrium Monte Carlo Sampling-Based Effective Algorithm for Fully-Connected Ising Models

Wang,

Jiang,

Zhang

et al. 2023

2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model

Cited by 4 publications

References 42 publications

Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI

Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI

2D router chip design, analysis, and simulation for effective communication

A Genuine-Equilibrium Monte Carlo Sampling-Based Effective Algorithm for Fully-Connected Ising Models

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