A near optimal scheduler for switch-memory-switch routers

Abstract

Routers are ubiquitous in modern computing, appearing in wide-area networks, multiprocessor servers, and data storage systems. Modern routers achieve high performance by solving computationally intensive tasks using custom hardware. One of the most challenging problems in designing a high-end router is scheduling the transfer of packets from inputs to outputs.We present a simple and near optimal randomized parallel scheduling algorithm for scheduling packets in routers based on the Switch-Memory-Switch (SMS) architecture, which emulates 'output queuing' by using a collection of small memories within the switch to buffer packets, and which forms the basis of the fastest routers in use today. Specifically, for a router with inputs and outputs, our algorithm computes the schedule inrounds, where a round is a communication of a few bits between input ports and memory together with simple local computation at the inputs and memory. Furthermore, by using andeep pipeline at each input, our algorithm computes the schedule in a constant number of rounds. Our pipelined algorithm is quite simple and achieves optimal (i.e., constant) throughput with a tiny ¡ £ ¢ ¤ § ¦ © delay. We show that the total amount of buffer memory required by our algorithm is close to the minimum required. We also show that the number of buffer memories is within an is the minimum number of memories needed under adversarial placement of packets. Furthermore we show that the number of extra memories that we use over the minimum of that is required in the offline version, is within a constant factor of the minimum required by any on-line scheduler, even if that scheduler is allowed to fail occasionally.Our scheduling algorithm is randomized and works with high probability in . We also prove that it has the 'self-stabilizing' property, i.e., it resumes its normal behavior if occasional lapses occur due to the probabilistic nature of the algorithm.

Accelerated Packet Placement Architecture for Parallel Shared Memory Routers

“…In [7], [8] Prakash, Sharif, and Aziz proposed the Switch-Memory-Switch (SMS) architecture, which is a variation on the PSM switch, as an abstraction of the M-series Internet core routers from Juniper. The approach consists of statistically matching input ports to memories, based on an iterative algorithm that statistically converges in O(logN ) time.…”

Randomized parallel schedulers for switch-memory-switch routers: analysis and numerical studies

“…We developed RiPSS [3]-a very simple randomized parallel scheduler for SMS routers-which we review in detail in Section II. In essence we proved that RiPSS computes a complete assignment of packets to memories in O(log * N ) basic matching rounds with high probability (w.h.p.…”

“…2) In [3] we presented a pipelined scheduling algorithm that uses an O(log * N ) deep pipeline of packets at the input to further reduce scheduler complexity compared to RiPSS. It requires only a constant number of rounds per cycle-independent of N and the input traffic patternin contrast to RiPSS, which requires O(log * N ) rounds per cycle.…”

“…However this algorithm requires both memories and inputs to send and process multiple messages. In this paper we present PRiPSS, an improved version of the pipelined scheduler in [3] that requires less communication and hardware. PRiPSS also uses an O(log * N ) deep pipeline of packets at the input and requires only constant number of rounds per cycle.…”

“…In this section we review germane results on SMS routers from our prior work [16], [3]. The SMS architecture is depicted in Figure 1.…”