Randomized parallel schedulers for switch-memory-switch routers: analysis and numerical studies

Abstract

Abstract-We present new results and numerical studies of very fast schedulers for SMS (Switch-Memory-Switch) routers, which emulate output-queuing by buffering packets in a partitioned shared-memory located between input and output ports. The architecture of Juniper's core routers and Brocade's storage switches is based on SMS.Our numerical results demonstrate that RiPSS, a randomized highly parallel SMS scheduler that we had developed recently, runs in just 3 rounds on switches with up to 4,096 inputs, and has a very low drop probability. We also show that RiPSS makes effective use of the shared-memory, with packets being uniformly distributed across the memory banks for both Bernoulli and bursty arrivals. We describe a new and improved randomized pipelined scheduler, PRiPSS, and analyze its performance. Both our analysis and our simulation results for PRiPSS show that it has better throughput than RiPSS with a slightly higher latency in terms of rounds of communication in the underlying hardware. Our analysis also shows that PRiPSS is self-stabilizing, i.e., if occasional lapses occur due to the probabilistic nature of the algorithm, it resumes normal behavior without the need for external intervention.While the choice of RiPSS or PRiPSS would depend on whether throughput or latency is the primary concern, our results indicate that both schedulers are much faster than other schedulers for output-queuing, whether implemented directly or through emulation on SMS.

Accelerated Packet Placement Architecture for Parallel Shared Memory Routers

“…In [7], [8] Prakash, Sharif, and Aziz proposed the Switch-Memory-Switch (SMS) architecture, which is a variation on the PSM switch, as an abstraction of the M-series Internet core routers from Juniper. The approach consists of statistically matching input ports to memories, based on an iterative algorithm that statistically converges in O(logN ) time.…”

How to Allocate Tasks Asynchronously

“…We follow the simple idea that when a process selects a task to execute, it should select randomly and nearly uniformly from the set of tasks not yet executed. This strategy is natural and appears periodically in the literature [8], [10], [12], [27]. We build a distributed data structure to perform the selection efficiently, and first analyze its randomized behavior.…”

Iteration-Shared Scheduling Algorithms Abolishing the Departure-Time-Compatible Graph in Switch-Memory-Switch Switches

“…Switch-Memory-Switch(SMS) architecture [11] [12][13] [14] exhibits an excellent performance over the competitors due to its emulating the Output Queueing (OQ) structure [15] and good scalability. In [11] [12], it is proved that with 2N-1 shared memories, a SMS switch can emulate a FIFO based OQ switch, and with 3N-2 shared memories, can emulate a general policy OQ switch.…”

“…Many scheduling algorithms [12][13] [14] were proposed to lighten the computation-consuming. However all the alternatives are too complex to be deployed in a high speed, especially large scale switch/router.…”