A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Zhang, Hui; Xia, Mingxin; Hu, Guangshu

doi:10.1109/tcsii.2006.886898

Cited by 54 publications

(37 citation statements)

References 5 publications

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“…Due to the significance of the GP as a fundamental processing primitive in computer vision, numerous non-conventional approaches aiming at boosting its hardware performance have also been reported [12], [13], [16]- [20]. Among them, mixedsignal focal-plane sensing-processing [12], [13], [16], [17] stands out as the best approach in terms of parallelization and energy efficiency.…”

Section: Gaussian Pyramid In Computer Visionmentioning

confidence: 99%

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The paper addresses a comparison of architectures for hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor frontend. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded pre-processing structures for Gaussian spatial filtering. This later choice belongs to the general category of "artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. The paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs (single-slope, SAR, cyclic, Σ∆ and pipeline), and the number of digital processors. Results show that speed and energy advantages of pre-processing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

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Section: Gaussian Pyramid In Computer Visionmentioning

confidence: 99%

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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“…Benkrid [9] proposed a 2D convolution core on FPGA in 2002. Later, Zhang [10] explored the different optimizations for FPGA-based convolution core on resource utilization, bandwidth, energy efficiency and memory access pattern. Recently, Chen [4] analyzed the design space and performance of a convolution layer based on the roofline model.…”

Section: Related Workmentioning

confidence: 99%

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

Zhao

Luk

et al. 2016

2016 IEEE 27th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Abstract-This paper presents a novel reconfigurable framework for training Convolutional Neural Networks (CNNs). The proposed framework is based on reconfiguring a streaming datapath at runtime to cover the training cycle for the various layers in a CNN. The streaming datapath can support various parameterized modules which can be customized to produce implementations with different trade-offs in performance and resource usage. The modules follow the same input and output data layout, simplifying configuration scheduling. For different layers, instances of the modules contain different computation kernels in parallel, which can be customized with different layer configurations and data precision. The associated models on performance, resource and bandwidth can be used in deriving parameters for the datapath to guide the analysis of design tradeoffs to meet application requirements or platform constraints. They enable estimation of the implementation specifications given different layer configurations, to maximize performance under the constraints on bandwidth and hardware resources. Experimental results indicate that the proposed module design targeting Maxeler technology can achieve a performance of 62.06 GFLOPS for 32-bit floating-point arithmetic, outperforming existing accelerators. Further evaluation based on training LeNet-5 shows that the proposed framework achieves about 4 times faster than CPU implementation of Caffe and about 7.5 times more energy efficient than the GPU implementation of Caffe.

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“…To balance the on-chip resources utilization and external memory bus bandwidth, the MWPB scheme [3] was proposed to reuse data that have already been stored in internal buffers. Fig.3 illustrates the proposed RD based MWPB architecture as a cascade of two MWPB convolvers.…”

Section: Rd Based Mwpb Architecturementioning

confidence: 99%

“…Designs for efficient FPGA implementations -achieving, say, a throughput of 1 pixel/clock mainly focus on two aspects: the design of the buffering scheme and improving the convolution kernel module. A good buffering scheme [2][3] can lead to reduced on-chip resources by limiting the number of input buffers based on an acceptable external memory bus bandwidth. Specifically, a full buffering (FB) scheme [2] would have an optimal external memory bus bandwidth of 1 pixel/clock, whilst a single-window partial buffering (SWPB) scheme [2] requires the least amount of on-chip resources; a multi-window partial buffering (MWPB) scheme [3] is a tradeoff between these two extremes.…”

Section: Introductionmentioning

confidence: 99%

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Yang

Bharath

2016

IEEE Trans. Circuits Syst. II

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Abstract-Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD) filter design method can reduce the computational complexity of 2-D convolutions by splitting the convolution between an image and a large mask into a sequence of convolutions using several smaller masks. This brief explores how to efficiently implement RD based 2-D convolvers using FPGA. Three FPGA architectures are proposed based on RD filters, each with a different buffering scheme. The conclusion is that RD based architectures achieve higher area efficiency than other previously reported state-of-the-art methods, especially for larger convolution masks. An area efficiency metric is also suggested, which allows the most appropriate architecture to be selected.Index Terms-Field-programmable gate arrays (FPGAs), large convolution mask, recurrently decomposable, two-dimensional (2-D) convolution.

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A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Cited by 54 publications

References 5 publications

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

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