A multiplication-free digital architecture for 16×16 2-D DCT/DST transform for HEVC

Area efficient DST architectures for HEVC

“…On the other hand, it requires double clock frequency to provide the same throughput, thus leading to higher power consumption. The last two columns of Table IV report the implementation details for the DST architectures proposed in [11], [12] as well. It is worth noting that the values for [11] refer to the implementation with input word length equal to 8 bits and the throughput has been calculated considering 4×4 DST blocks.…”

“…However, while several architectures have been recently proposed for the integer DCT specified in HEVC [8]- [10], only few works address the design of hardware architectures to efficiently compute the integer DST. Edirisuriya et al [11] exploited the relationships between the DCT of different sizes and the DST to design a multiplication-free architecture, which is able to perform both the DCT and the DST on a block of size up to 16×16 samples. However, the reconfigurability of the system to support different transforms is paid in terms of large area occupation due to an high number of hardware resources, which are not fully utilized.…”

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

“…Table I shows the hardware overhead comparisons of our proposed 1-D Transformation core with other 1-D HEVC DCT/IDCT architectures. Thereinto, reference [6] and [5]'s architectures are implemented with FPGA, and the gate counts are their LUT numbers.…”

“…According our evaluation, its hardware utilization is lower than 20%. According to the table, the hardware utilization rates of reference [6], reference [5] and reference [7] are much higher than others. However, the performance of these parallel architectures with huge throughput far exceed their practical requirements.…”

“…R. Jeske also presented a 16-point 1-D DCT multiplierless hardware architecture for HEVC in 2012 [5]. Based on approximation DCT algorithm, A. Edirisuriya proposed a multiplicationfree architecture for 16×16 point approximation HEVC 2-D DCT/DST transform in 2012 [6]. To support large size IDCT, J.S.…”