A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

“…As can be seen, the standard deviation of SAE timing generated by pipelined circuit obtains 69.45% improvement compared with that generated by conventional circuit, owing to 235.89 ps reduction. Generally, the delay time of the SAE timing occupies about half of the cycle time [5,6,7,9,10]; hence, the conventional cycle time is 10.52 ns (ð6:26 À 1Þ ns  2). According to [5,6,7,9,10], three-sigma (3) variation existing is assumed for the SAE timing margin; thus, the SAE timing margin is reduced from 2.038 ns (3  2) to 0.623 ns by applying the proposed circuit.…”

“…Hence, the final standard deviation of proposed SAE timing can be expressed as ffiffiffiffi ffi M p Conv =N. Especially, assume that N remains constant, when M ¼ 1, the standard deviation of proposed SAE timing is also equal to Conv =K, which is the same as that with parallel replica-bitline Delay addition (MPRDA) technique [10]. The major difference (e.g.…”

“…However, with the variations of process, voltage and temperature (PVT) existing, the accurate SAE timing is necessary for reliable operation [1,2,3,4,5,6,7,8,9,10]. In order to obtain the optimum timing for SAE, based on the replica bitline (RBL) technique [3], some timing generation circuits [4,5,6,7,8,9,10] were proposed. Reference [5] gives the analyzation of the existing techniques, and proposes an efficient RBL technique without area-overhead.…”

Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers

“…If the SAE arrives early before the bitline voltage difference reaches the SA offset, a read failure may happen. By contrast, unnecessary access time and power consumption will be increased [2][3][4][5]. Generally, the SAE signal is self-timed using the replica bitline (RBL) technique, since it tracks bitline delay better than simple inverter chains [2].…”

“…In [4], with the usage of K times RCs in a replica column and timing multiplier circuit (TMC), a digitised RBL delay (digitised-RBD) technique has been developed. The disadvantage of this scheme is that the quantisation noise as well as the area of the TMC becomes larger as the count of RCs increases [5]. With the RBL segmented into M stages and K times RCs used in each stage, another technique called multiple-stage parallel RBL delay addition is proposed in [5].…”