Abstract. Architectures for focal plane image processing are discussed. On-chip image preprocessing for solid-state imagers using analog CCD circuits is described for low, medium, and high density detector arrays. A spatially parallel architecture for low density, high throughput applica tions is described. For sparse illumination or event detection, a content· addressable architecture is proposed. A new pipelined vector pixel pro· cessor architecture for medium density infrared staring focal plane ar rays is described. Neighborhood reconstruction during serial readout of high density TV-quality imagers for a pixel processor is considered using delay and analog frame memory techniques. The potential of on-chip read/write analog frame memory for image transformation and frame·to frame processing is discussed.