A multi-step etch method for fabricating slightly tapered through-silicon vias based on modified Bosch process

Lin, Puru Bruce; Xie, Xiaochen; Wang, Yong; Lian, Binhao; Zhang, Guoqi

doi:10.1007/s00542-018-4249-8

Cited by 6 publications

(5 citation statements)

References 13 publications

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“…To our best knowledge, such an extended scalloping has never been reported in the literature for the Bosch process. Nevertheless, some increased sidewall roughness or damage has been reported under specific circumstances by several authors [ 24 , 26 , 28 , 29 , 30 , 31 ]. It is, in most cases, due to non-normal ion bombardment or when the sidewalls are positive [ 26 , 28 ], which weakens the passivation layer and enhances locally the etch.…”

Section: Resultsmentioning

confidence: 99%

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

et al. 2021

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The cryogenic process is well known to etch high aspect ratio features in silicon with smooth sidewalls. A time-multiplexed cryogenic process, called STiGer, was developed in 2006 and patented. Like the Bosch process, it consists in repeating cycles composed of an isotropic etching step followed by a passivation step. If the etching step is similar for both processes, the passivation step is a SiF4/O2 plasma that efficiently deposits a SiOxFy layer on the sidewalls only if the substrate is cooled at cryogenic temperature. In this paper, it is shown that the STiGer process can achieve profiles and performances equivalent to the Bosch process. However, since sidewall passivation is achieved with polymer free plasma chemistry, less frequent chamber cleaning is necessary, which contributes to increase the throughput.

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Section: Resultsmentioning

confidence: 99%

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

et al. 2021

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“…Then the t-RIE step was performed (Alcatel dry etcher). The scallops typical of the deep reactive ion etching (DRIE) , may be strong pinning sites for droplets and frustrate the self-ejection. Therefore, we opted for continuous etching , using SF 6 -C 4 F 8 plasma, a process without scallops and in which the ratio of gas flows, chamber pressure, bias and source power, and temperature influence the tapering and uniformity of the sidewalls.…”

Section: Methodsmentioning

confidence: 99%

Single Condensation Droplet Self-Ejection from Divergent Structures with Uniform Wettability

Di Novo,

Bagolini,

Pugno

2024

ACS Nano

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Coalescence-induced condensation droplet jumping has been extensively studied for anti-icing, condensation heat transfer, water harvesting, and self-cleaning. Another phenomenon that is gaining attention for potential enhancements is the self-ejection of individual droplets. However, the mechanism underlying this process remains elusive due to cases in which the abrupt detachment of an interface establishes an initial Laplace pressure difference. In this study, we investigate the self-ejection of individual droplets from uniformly hydrophobic microstructures with divergent geometries. We design, fabricate, and test arrays of truncated, nanostructured, and hydrophobic microcones arranged in a square pattern. High-speed microscopy reveals the dynamics of a single condensation droplet between four cones: after cycles of growth and stopped self-propulsion, the suspended droplet self-ejects without abrupt detachments. Through analytical modeling of the droplet in a conical pore as an approximation, we describe the slow isopressure growth phases and the rapid transients driven by surface energy release once a dynamic configuration is reached. Microcones with uniform wettability, in addition to being easier to fabricate, have the potential to enable the self-ejection of all nucleated droplets with a designed size, promising significant improvements in the aforementioned applications and others.

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“…The implementation of 3D technology helps alleviate problems associated with interconnection delays by reducing gate delays and increasing interconnections through the use of shorter wires. These shorter wires help reduce the average load capacitance and resistance, resulting in a decrease in the number of repeaters required to regenerate the signal on long wires [1,2]. Vertical stacking of ICs has become a viable option in the semiconductor industry for reducing wirelength and integration.…”

Section: Introductionmentioning

confidence: 99%

“…Vertical stacking of ICs has become a viable option in the semiconductor industry for reducing wirelength and integration. For example, stacking capacitance and resistance, resulting in a decrease in the number of repeaters required to regenerate the signal on long wires [1,2]. Vertical stacking of ICs has become a viable option in the semiconductor industry for reducing wirelength and integration.…”

Section: Introductionmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

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A multi-step etch method for fabricating slightly tapered through-silicon vias based on modified Bosch process

Cited by 6 publications

References 13 publications

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

Single Condensation Droplet Self-Ejection from Divergent Structures with Uniform Wettability

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

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