A multi-standard flexible turbo/LDPC decoder via ASIC design

Gentile, Giuseppe; Rovini, Massimo; Fanucci, Luca

doi:10.1109/istc.2010.5613886

Cited by 25 publications

(18 citation statements)

References 14 publications

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“…Compared with the works capable of supporting multiple standards [3,5,6], the throughput (TP) can gain up to about 10Â improvement, and the ratio of throughput and area (TAR) can be improved up to about 25Â. These improvements mainly result from the simple memory structure and permutation network, which can increase the frequency of the decoder and exploit the parallelism of the decoding process to improve the throughput of the decoder.…”

Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

“…Some studies have attempted to implement the multi-standard decoders on ASIC. Giuseppe Gentile, et al proposed a SIMD-based decoder on ASIC to support WiMAX and WiFi standards by means of the shared memory [3], however, the implementation of the memory management unit is a challenge. Chih-Hao Liu, et al implemented a multimode decoder with a reconfigurable message-passing network to support WiMAX and WiFi standards [4], however, the performance degradation resulted from the complex permutation network.…”

Section: Introductionmentioning

confidence: 99%

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An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

Guo

Dou

Lei

et al. 2015

IEICE Electron. Express

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This paper presents an efficient multi-standard decoder for quasicyclic low-density parity-check (QC-LDPC) codes. By employing the configurable multi-bank memory structure, simplified permutation network and multiple pipelined datapaths, the decoder can efficiently support WiMAX and WiFi standards without any structural changes. The offset-min-sumbased row-layered decoding algorithm is adopted to reduce the computation complexity. Based on these optimizations, the proposed decoder can achieve about 658 Mbps (1410 Mbps) and 527 Mbps (1129 Mbps) for WiMAX and WiFi standards on TSMC 130 nm (and 65 nm) Application Specific Integrated Circuits (ASICs) platforms, respectively. Compared with the previous works, the throughput can obtain up to 10× improvement for WiMAX standard and 5× improvement for WiFi standard.

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Section: Performance Evaluation and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

Guo

Dou

Lei

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…To the best of our knowledge, no implementation solution for the concatenated scheme has been proposed so far, but decoders for both turbo and LDPC codes are present in the state of the art, mainly targeting wireless communications. Multicode and multistandard decoders that make flexibility their primary concern have also been introduced recently [8][9][10][11][12][13]; they are characterized by different degrees of datapath and memory sharing.…”

Section: Introductionmentioning

confidence: 99%

Unified turbo/LDPC code decoder architecture for deep-space communications

Condo

Masera

2014

IEEE Trans. Aerosp. Electron. Syst.

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Deep-space communications are characterized by extremely critical conditions; current standards foresee the usage of both turbo and low-density-parity-check (LDPC) codes to ensure recovery from received errors, but each of them displays consistent drawbacks. Code concatenation is widely used in all kinds of communication to boost the error correction capabilities of single codes; serial concatenation of turbo and LDPC codes has been recently proven effective enough for deep space communications, being able to overcome the shortcomings of both code types. This work extends the performance analysis of this scheme and proposes a novel hardware decoder architecture for concatenated turbo and LDPC codes based on the same decoding algorithm. This choice leads to a high degree of datapath and memory sharing; postlayout implementation results obtained with complementary metal-oxide semiconductor (CMOS) 90 nm technology show small area occupation (0.98 mm 2 ) and very low power consumption (2.1 mW).

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“…The supported types in turbo are usually Single Binary and/ Double Binary Turbo Codes (SBTC and DBTC). The ASIC based flexible architecture presented in [2] can support multiple standards (HSDPA, WiMAX, Wi-Fi, DVB-H) with LDPC and turbo coding options. However, it occupies a large area of 0.9mm 2 in 45nm technology ( 3.6mm 2 in 90nm).…”

Section: Introductionmentioning

confidence: 99%

“…The achieved throughput is comparable to[1] in LDPC Wi-Fi mode while UDec achieves 75Mbps more in LDPC WiMAX mode. In turbo mode, the UDec throughput is more than 5 times that achieved by[1] at cost of twice the occupied area (after technology normalization) [2]. occupies 28% more area compared to UDec and does not achieve the throughput requirement of LTE.…”

mentioning

confidence: 98%

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

Murugappa¹,

Al-Khayat²,

Baghdadi³

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. This paper presents a multi-core architecture which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes. The proposed architecture is based on Application Specific Instruction-set Processors (ASIP) and avoids the use of dedicated interleave/deinterleave address lookup memories. Each ASIP consists of two datapaths one optimized for turbo and the other for LDPC mode, while efficiently sharing memories and communication resources. The logic synthesis results yields an overall area of 2.6mm 2 using 90nm technology. Payload throughputs of up to 312Mbps in LDPC mode and of 173Mbps in Turbo mode are possible at 520MHz, fairing better than existing solutions.

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A multi-standard flexible turbo/LDPC decoder via ASIC design

Cited by 25 publications

References 14 publications

An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

Unified turbo/LDPC code decoder architecture for deep-space communications

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

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