A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

Abstract

In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. This paper presents a multi-core architecture which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes. The proposed architecture is based on Application Specific Instruction-set Processors (ASIP) and avoids the use of dedicated interleave/deinterleave address lookup memories. Each ASIP consists of two datapaths one optimized for turbo and the other for LDPC mode, while efficiently sharing memories and communication resources. The logic synthesis results yields an overall area of 2.6mm 2 using 90nm technology. Payload throughputs of up to 312Mbps in LDPC mode and of 173Mbps in Turbo mode are possible at 520MHz, fairing better than existing solutions.

The improved Turbo-decoding Message-passing algorithm and corresponding decoder for LDPC based on LTE

“…In this paper, we use a FPGA-based prototype of a communication system presented in [11], which demonstrated the effectiveness of Application-Specific Instruction-set Processor (ASIP) concept in the implementation of flexible multi-standard platforms for wireless communications. The architecture has 4 A N = ASIPs, each processing 2 A CN = check nodes per clock cycle [12].…”

“…Comparing equation (13) with equation(11), we can see that the errors of prior messages are partially eliminated. Especially, when the first layer's prior messages of one iteration update, all the errors come from the previous iteration.…”

Adapted scheduling of QC-LDPC decoding for multistandard receivers

“…100 Mbps at 140 MHz). Other teams [7] [8] are working on an ASIP chipset able to decode LDPC, bTC and dbTC but requiring to be reconfigured between different usages. [9] proposes a turbodecoding architecture to merge a LDPC and a bTC decoder.…”

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

“…The extrinsic information is iteratively and concurrently exchanged between multiple component decoders via an on-chip communication network presented in [15]. Afterwards, an optimized implementation of the ASIP supporting both turbo codes and LDPC codes, called DecASIP have been presented in [16]. Similarly, the authors in [17] introduce the FlexiTreP ASIP presented in [18] in a multi-ASIP architecture for turbo decoding to reach the 150 Mbps throughput requirement of LTE.…”

“…The authors of [22] propose a dynamically reconfigurable ASIP-based architecture for turbo decoding allowing reconfiguration of the entire platform during the current decoding task in order to propose a frame by frame dynamic configuration. This architecture has been optimized based on the initial work presented in [16]. Up to 64 processors are reconfigured using a bus-based configuration infrastructure implementing optimized transfer mechanisms.…”