A Multi-Stage Fault-Tolerant Multiplier With Triple Module Redundancy (Tmr) Technique

Abstract

In this study, a multistage fault-tolerant (MSFT) scheme for two¯xed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost faulttolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-m CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 Â 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 Â 64 Type-I MSFT multiplier is only 0:21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 Â 64 Type-II MSFT multiplier

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

“…The measurement results indicate that the triple-TDC achieves a time resolution of the 40 ps root mean square (RMS) for multimode operation. The triple modular redundancy (TMR) scheme [32] is used to improve the uncertainty in the FPGA device for single-mode operation, such as the UWB effect. The TMR triple-TDC can achieve a resolution of 35.5 ps RMS and improve INL and DNL values by an average of 56% and 37%, respectively.…”