A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling

Liu, Litong; Jin, Jing; Liu, Xiaoming; Zhou, Jianjun

doi:10.1109/tcsii.2020.2983785

Cited by 3 publications

(1 citation statement)

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“…In order to strengthen the applicability of the clock generator by increasing the loop divider ratio, methods such as compressing the reference clock frequency range and expanding the divider ratio of MMD can be implemented. Prior research generally confirms that the division ratio extension is invariably achieved by improving two dimensions of integer or fractional-N division accuracy [11,12]. While the MMD is composed of the prescalers and the counters expand the logic control bit width of the counter, the consumption of hardware cannot be ignored.…”

Section: Introductionmentioning

confidence: 95%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

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Section: Introductionmentioning

confidence: 95%