A MOSFET with Si-implanted gate-SiO/sub 2/ insulator for nonvolatile memory applications

Abstract

A MOSFET with Si-implanted gate-SiO, insulator (MEmory-Insulator Transistor MEIT) is fabricated and investigated, especially with emphasis on its feasibility. for nonvolatile memory applications for the first time. A highdose Si' implantation to thermal SiO, introduces excess-Si cites acting as traps responsible for a memory effect. 14s a result, a large Vr window of -10 V is achieved by applying small electric fields of 3-5 MV/cm to the MEIT insulator fof write/erase programming. By taking advantage of the memory effect, it is found that MEIT achieves sufficient programming characteristics as a Flash EPROM as well as simplicity of the single poly-Si-gate process. Most of all, the V, window is scarcely degraded, at least, up to lo7 write/ erase cycles. Although further investigation is needed, MEIT is promising for nonvolatile memory applications. 0. 103.0 $ F 103.2 103.4 e z ) r W CD c Si + implantation + + $ . I Drain ) \Source/ Fig.1 Process sequence of a METTFET. The typical Si+ imlplant dose is 1~1 0 '~ cm".

Memory characteristics of Al nanocrystals embedded in Al2O3 layers

“…Metal nanocrystals can be utilized for the fabrication of nonvolatile memory devices by making use of localized trap sites, due to their remarkable properties including the Coulomb blockade effect and the controllable size [1,2]. The nanocrystals are embedded as charge-storage nodes between a control oxide layer and a tunneling oxide layer in order to replace continuous floating gate layers used in conventional flash memory devices.…”

The Synthesis of Silicon Nanocrystals by Ion Implantation

“…This shows the annealing behavior of nanocrystals in an 8 nm thick SiO 2 on Si after implantation with 1 keV Si ions to a fluence of 2 Â 10 15 Si cm À2 . This is an important consideration for nonvolatile memory (NVM) applications where the nanocrystals are charged and discharged by electron tunneling to the substrate [29]. A separate study has shown that the width of such denuded zones can be controlled by suitable choice of the implantation and annealing conditions [28].…”

Comparison of interface trap density measured by capacitance/subthreshold/charge-pumping methods for n-MOSFETs with Si-implanted gate-SiO/sub 2/

“…The combined interface trap charge per cycle Qss is given by (17) where &(=lo4 cm') is the gate area of MOSFET, v*(=107 cm/s) is the thermal verocity, 0,(=6.5xlO-~~ cm2) and a,(=2.4~10-'~ cm2) are the capture cross sections of electron and hole, AV,(= 6V) is the pulse amplitude, a(= 0.5) is the fraction of the rise time [26],According to (16) and (17), a mean interface trap density D,, distributed between V, and V, can be extracted by the measurement of charge-pumping current Im.…”

“…The Si-implantation was selected because it produces traps and states in the SiOz and/or SiOz-Si interface, and affects the current-voltage (I -V) curves in heavy dose cases [12-141. Furthermore, MOSFETs with heavy Siimplanted SiOz exhibit hysteresis in the I -V curve due to the trap-like behavior of excess Si atoms and offer a possibility of a non-stacked EEPROM or flash memory [15][16][17]. Recently, it was reported that the Si-implanted MOS capacitor exhibited visible electro-luminescence and might be useful for a light emitting device which has process compatibility with Si LSIs [18, 191. However the effects of heavy Si implantation into the gate-SiOz on Dit have not been extensively studied until now.…”