A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit

Lai, B.; Walker, Richard

doi:10.1109/isscc.1991.689102

Cited by 38 publications

(16 citation statements)

References 2 publications

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“…At the output of the filter , this input signal results in (6) where is the dc component of . Since the input to the quantizer is the solution to (6) at , the metastable output condition can only occur when (7) This can be rearranged as (8) This implies that if we keep constant, then becomes directly proportional to the dc component, , of the input signal that causes the sampler to become metastable. Simulating to find this value provides the required indirect measurement of the filter .…”

Section: Sampler Impulse Responsementioning

confidence: 99%

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A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

Ierssel

Sheikholeslami

Tamura

et al. 2007

IEEE J. Solid-State Circuits

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Abstract-This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.

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Section: Sampler Impulse Responsementioning

confidence: 99%

“…This approach, however, does not apply to the nonlinear behavior of bang-bang [8] simulations. These simulations are often of long duration due to the CDR loop filter having a bandwidth that is orders of magnitude lower than the operating frequency.…”

mentioning

confidence: 99%

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

Ierssel

Sheikholeslami

Tamura

et al. 2007

IEEE J. Solid-State Circuits

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“…Then, this filter (figure 1) can be used for clock recovering by filtering the harmonic components [8,9]. It can also be employed as bandpass filter centered around Fo.…”

Section: Architecture Of the Proposed Filtermentioning

confidence: 99%

A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications

Oualkadi

Paillot

Belkouch

et al. 2007

2007 14th IEEE International Conference on Electronics, Circuits and Systems

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This paper would like to prove the feasibility of a new high-Q eight-path bandpass filter. The proposed filter is tuned by using a command circuit made up by a ring voltage controlled oscillator (VCO) with 'XOR' gates. Fabricated in a standard 0.35 µm CMOS, this circuit is intended to replace the SAW filters in wireless broadband applications. Experimental results demonstrate interesting performances; a tunable center frequency range of 200 MHz [300-500 MHz] and a quality factor that can be as high as 200 within the tunable frequency range.

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“…Then, this filter can be used for clock recovering by filtering the harmonic components [6,7]. It can also be used as bandpass filter centered around Fo.…”

Section: Architecture Of the Proposed Filtermentioning

confidence: 99%

Novel LC pseudo switched capacitor filter suited for wireless RF applications

Oualkadi

Paillot

Guegnaud³

2005

IEICE Electron. Express

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Switched capacitor filters have been in wide-spread used for a few years, for the realization of stable, accurate and high quality filters for operating frequencies below the megahertz range. This paper would like to prove the feasibility of a novel tuned LC pseudo switched capacitor filter with high quality factor of several hundreds for wireless radio frequency applications. The filter is designed with standard 0.35 µm silicon BiCMOS technology. Experimental results at 442 MHz switching frequency demonstrate interesting performances; the quality factor is equal to 316 for a frequency bandwidth equals to 1.4 MHz.

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A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit

Cited by 38 publications

References 2 publications

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications

Novel LC pseudo switched capacitor filter suited for wireless RF applications

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