A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

Abstract

Abstract-This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.

An all-digital semi-blind clock and data recovery system

“…The main difference between the proposed design and the design in [9] is the embedded ADPLL. This ADPLL in the proposed SBCDR has negligible effect on JTo.…”

“…Both limitations are described in Fig. 5 (a) and (b) for IR ¼4 and OSR¼ 5 and are discussed in more details in [9]. The proposed phase exclusion algorithm eliminates these two limitations.…”

“…8(b). The need of the elastic FIFO and the utilization of the ADD/DROP signals are discussed in [9].…”

“…Eq. (1) describes the JTo OS over the three frequency regions [9]. The frequency thresholds F C1 , and F C2 are described in Eqs.…”

“…The sampling clock is no longer a data independent internal clock, it is rather a recovered clock that tracks the received data phase. This provides low frequency jitter and frequency error tolerance [9]. The SBCDR loop is similar to a conventional phase tracking CDR such as phase locked loop CDR [6].…”