A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

Srinivasa, Srivatsa; Ramanathan, Akshay Krishna; Li, Xueqing; Chen, Wei-Hao; Hsueh, Fu-Kuo; Yang, Chih-Chao; Shen, Chang‐Hong; Shieh, Jia‐Min; Gupta, Sumeet Kumar; Chang, Meng‐Fan; Ghosh, Swaroop; Sampson, Jack; Narayanan, Vijaykrishnan

doi:10.1145/3218603.3218645

Cited by 13 publications

(2 citation statements)

References 16 publications

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“…Aga et al extend this work in their iSC architecture by noring the two BLs, resulting in a xor operation [5]. This architecture forms the basis of many iSC publications [6], [9], [24], [25], [26], [27].…”

Section: Wordlines (Wl)mentioning

confidence: 99%

“…A third method is to use pulse width modulated WLs such that no two WLs are active simultaneously [28], removing the danger of data corruption, but at the cost of a 2.35x increase in periphery area. Finally, nonconventional technologies can be used, such as monolithic 3D integration [25], [26], or deeply depleted channel technology [36]. Emerging technologies present their own challenges however; for example, DDC technology demonstrates stability issues [37] and disturb risks, and results in poor performance/voltage scaling (100Mhz@0.6V.…”

Section: Avoid Data Corruption While Maintaining High Operating Frequmentioning

confidence: 99%

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BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

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Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spatially local data common in many emerging workloads, while reducing power consumption due to data movement. However, in-SRAM computing faces many challenges, including integration into the existing architecture, arithmetic operation support, data corruption at high operating frequencies, inability to run at low voltages, and low area density. To meet these challenges, this work introduces BLADE, a BitLine Accelerator for Devices on the Edge. BLADE is an in-SRAM computing architecture that utilizes local wordline groups to perform computations at a frequency 2.8x higher than state-of-the-art in-SRAM computing architectures. BLADE is integrated into the cache hierarchy of low-voltage edge devices, and simulated and benchmarked at the transistor, architecture, and software abstraction levels. Experimental results demonstrate performance/energy gains over an equivalent NEON accelerated processor for a variety of edge device workloads, namely, cryptography (4x performance gain/6x energy reduction), video encoding (6x/2x), and convolutional neural networks (3x/1.5x), while maintaining the highest frequency/energy ratio (up to 2.2Ghz@1V) of any conventional in-SRAM computing architecture, and a low area overhead of less than 8%.

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Section: Wordlines (Wl)mentioning

confidence: 99%

Section: Avoid Data Corruption While Maintaining High Operating Frequmentioning

confidence: 99%

BLADE: An in-Cache Computing Architecture for Edge Devices

Simon

Qureshi

Rios

et al. 2020

IEEE Trans. Comput.

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Aggressive GPU cache bypassing with monolithic 3D-based NoC

Thuan

Kim²,

Chung³

2022

J Supercomput

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Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

Wang

Zhang

et al. 2021

iScience

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Summary Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS 2 transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR / XOR computations and the skewed SRAM cell can achieve in-memory NAND / NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

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A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support

Cited by 13 publications

References 16 publications

BLADE: An in-Cache Computing Architecture for Edge Devices

BLADE: An in-Cache Computing Architecture for Edge Devices

Aggressive GPU cache bypassing with monolithic 3D-based NoC

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

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