A modular simulation framework for architectural exploration of on-chip interconnection networks

Kogel, Tim; Doerper, Malte; Wieferink, Andreas; Leupers, Rainer; Ascheid, Gerd; Meyr, H.; Goossens, Serge

doi:10.1145/944646.944648

Cited by 24 publications

(12 citation statements)

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“…Here, traces are measured once and taken for the computation of performance and resource utilization. Case studies and other approaches [211] have demonstrated the modeling accuracy even for complex buses and Network-on-Chips (NoCs) [212]. Further research has even broadened the investigated communication impact to evaluate the cost of control operations [213].…”

Section: Joint Analytical and Simulation-based Approachesmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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Section: Joint Analytical and Simulation-based Approachesmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

Self Cite

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“…The timing assumption is explicit and untimed (the delays of links must be specified in absolute time units, NoC has no awareness of a common time reference). A similar approach was presented by Kogel et al [9], with data processed at transaction level by a network engine that can implement high-level behaviour of point-to-point, bus-based, and crossbar interconnects. Coppola et al [10] presented OCCN, a modeling and simulation framework that features a layered model for inter-module communication, with each layer translating transaction requests to a lower-level protocol.…”

Section: Related Workmentioning

confidence: 99%

A flexible network-on-chip simulator for early design space exploration

Grecu¹,

Ivanov²,

Saleh³

et al. 2008

2008 1st Microsystems and Nanoelectronics Research Conference

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Abstract-The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

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“…Kogel [1] and Pasricha [2], for example, have recently presented tools for early exploration of bus-based on-chip communication architectures. They show that such exploration early in the design is essential for developing efficient implementations.…”

Section: Previous Workmentioning

confidence: 99%

Communication strategies for shared-bus embedded multiprocessors

Bambha

Bhattacharyya

2005

Proceedings of the 5th ACM International Conference on Embedded Software

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This paper explores the problem of efficiently ordering interprocessor communication operations in both statically and dynamically-scheduled multiprocessors for iterative dataflow graphs with probabilistic execution times. In most digital signal processing applications, the throughput of the system is significantly affected by communication costs. We explicitly model these costs within an effective graph-theoretic analysis framework. We show that ordered transaction schedules can significantly outperform both self-timed schedules and dynamic schedules for moderate task execution time variability. As the task execution time variability increases, we show that first self-timed and then dynamic scheduling policies are preferred. We perform an extensive experimental comparison on both real and simulated benchmarks to gauge the effect of synchronization and communication overhead costs on these crossover points.

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A modular simulation framework for architectural exploration of on-chip interconnection networks

Cited by 24 publications

References 0 publications

Multiprocessor Systems on Chip

Multiprocessor Systems on Chip

A flexible network-on-chip simulator for early design space exploration

Communication strategies for shared-bus embedded multiprocessors

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