A Modular Memory BIST for Optimized Memory Repair

Oehler, P.; Bosio, Alberto; Natale, Giorgio Di; Hellebrand, Sybille

doi:10.1109/iolts.2008.30

Cited by 6 publications

(1 citation statement)

References 5 publications

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“…Also the hardware complexity for the mustrepair analysis is only quadratic with respect to the number of repair elements. However, in this method, repeating the complete test for possible solutions may lead to a high increase in test time [8]. For existing optimal analyzers [4], [6], as well as our analyzer, Figure 1 shows the number of test sessions and CAM entries required for the repair analysis.…”

Section: Introductionmentioning

confidence: 99%

Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate

Chung

Park

Abraham³

et al. 2010

2010 28th VLSI Test Symposium (VTS)

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This paper presents a built-in self repair analyzer with the optimal repair rate for embedded memory arrays. The proposed method requires only a single test, even in the worst case. By performing the must-repair analysis on the fly during the test, it selectively stores fault addresses, and the final analysis to find a solution is performed on the stored fault addresses. To enumerate all possible solutions, existing techniques use depth first search using a stack and a FSM. Instead, we propose a new algorithm and its combinational circuit implementation. Since our formulation for the circuit allows us to use the parallel prefix algorithm, it can be configured in various ways to meet area and test time requirements. The total area of our infrastructure is dominated by the number of CAM entries to store the fault addresses, and it only grows quadratically with respect to the number of repair elements.

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Section: Introductionmentioning

confidence: 99%