A Modified SRAM Based Low Power Memory Design

Sachan, Divyesh; Peta, Harish; Goswami, Manish

doi:10.1109/vlsid.2016.80

Cited by 15 publications

(5 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The BL and BLB lines are connected to the sense amplifier to sense the nodal values without killing the memory data in the cell. The sense amplifier amplifies the minimum difference sensed between the memory nodes and amplifies it so that the data is read by the peripheral circuits [4][5].…”

Section: Conventional Sram Cell (6t Sram Cell)mentioning

confidence: 99%

Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

Jagadale¹,

Phapale²,

Bhaaskaran³

2018

IJET

View full text Add to dashboard Cite

Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con-sumption through the use of cell control circuit.

show abstract

Section: Conventional Sram Cell (6t Sram Cell)mentioning

confidence: 99%

Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

Jagadale¹,

Phapale²,

Bhaaskaran³

2018

IJET

View full text Add to dashboard Cite

show abstract

“…Research shows that embedded SRAM contributes to over 30% of the system power consumption of a mobile device [2,3]. Researchers are working towards designing new low power devices due to the increasing amount of portable device usage [4], but viewer experience is rarely considered when developers are trying to improve hardware design to save power.…”

Section: List Of Tablesmentioning

confidence: 99%

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

Gao¹,

McCourt²,

Wang³

et al. 2018

View full text Add to dashboard Cite

“…To improve the performance of SRAM memory in these situations, different SRAM cells such as 9T, 5T, 7, and 6T SRAM cells in [6][7][8][9][10] and 10T, 12T, 7, and 10T SRAM cells in [11][12][13][14][15] have been presented. Among referenced cells, cells in [6][7][8][9][10], contrary to cells in [11][12][13][14][15], are not compatible with bit interleaving structure. The performance of the cells in [6][7][8][9][10] improves with different techniques such as weakening feedback, isolating storage node of disturbances, eliminating driver transistor, and separating read and write operation paths.…”

Section: Introductionmentioning

confidence: 99%

“…Among referenced cells, cells in [6][7][8][9][10], contrary to cells in [11][12][13][14][15], are not compatible with bit interleaving structure. The performance of the cells in [6][7][8][9][10] improves with different techniques such as weakening feedback, isolating storage node of disturbances, eliminating driver transistor, and separating read and write operation paths. The mentioned techniques also have been used in the bit interleaving cells in [11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…The standard 6T cell does not follow bit interleaving structure and does not deliver a good performance in sub‐threshold region and in smaller technologies. To improve the performance of SRAM memory in these situations, different SRAM cells such as 9T, 5T, 7, and 6T SRAM cells in [6–10] and 10T, 12T, 7, and 10T SRAM cells in [11–15] have been presented. Among referenced cells, cells in [6–10], contrary to cells in [11–15], are not compatible with bit interleaving structure.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

Nobakht

Niaraki

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

show abstract

A Modified SRAM Based Low Power Memory Design

Cited by 15 publications

References 6 publications

Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

Viewer-Aware Intelligent Mobile Video System for Prolonged Battery Life

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

Contact Info

Product

Resources

About