Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con-sumption through the use of cell control circuit.