A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

Ooishi, T.; Komiya, Yuichiro; Hamade, K.; Asakura, M.; Yasuda, Katsuhiro; Furutani, K.; Kato, T.; Hidaka, Hideto; Ozaki, H.

doi:10.1109/4.499735

Cited by 6 publications

(2 citation statements)

References 17 publications

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“…Therefore, there is a trade-off between the PSRR and the efficiency of LDOs [47]. Researchers are focused on developing synchronous digital LDOs to overcome this issue [48,49]. A digital error amplifier is in the synchronous digital LDO, and an external sampling clock is used in the feedback controller and the comparator [50].…”

Section: Reducing Noise Levels Furthermentioning

confidence: 99%

Current Context and Research Trends in Linear DC–DC Converters

et al. 2022

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With the introduction of switch-mode power supplies (SMPS) in the mid-1970s, the efficiency of DC–DC conversion rose from 60 to 80% and SMPS became a popular power supply solution. However, linear regulators have not become obsolete. The modern power management system in portable devices supports a complex mix of DC–DC converters, combining switch-mode power supplies (SMPS), switched capacitor converters (SCCs), and linear regulators in the form of low-dropout regulators (LDOs). LDOs are used to supply low-voltage DC power rails with very low noise and high current slew rate capability, which are usually fed by the output rail of SMPS. This paper provides a comprehensive review of the evolution of the application scope of linear-type DC–DC converters in the power supply context and the present research trends. First, we review the context of linear DC–DC converters in detail, particularly in portable device power supplies. Then, the details of LDO regulators and their recent industry development and research trends are discussed. Then, the discussion focuses on supercapacitor-assisted low-dropout (SCALDO) regulator design and its scope in the portable device power management together with SCALDO-based dual output and reduced switch designs, and finally, the conclusions follow.

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Section: Reducing Noise Levels Furthermentioning

confidence: 99%

Current Context and Research Trends in Linear DC–DC Converters

et al. 2022

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“…To address the aforementioned issues of analog LDOs, the predominant design trends of LDOs have been shifted from analog to digital in current state-of-the-art SoC devices in deep submicron CMOS processes. The first work proposed in this domain was a digital-assisted analog LDO that employed a parallel topology of an analog and digitally controlled pass transistors for powering a DRAM [34]. Another digitalassisted analog LDO was proposed for biasing a DC-DC converter [35].…”

Section: Synchronous Digital Ldomentioning

confidence: 99%

Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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Voltage Down-Converters

Itoh

Horiguchi

Tanaka

Series on Integrated Circuits and Systems

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A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

Cited by 6 publications

References 17 publications

Current Context and Research Trends in Linear DC–DC Converters

Current Context and Research Trends in Linear DC–DC Converters

Architectural Advancement of Digital Low-Dropout Regulators

Voltage Down-Converters

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