A mixed dispatching rule for semiconductor wafer fabrication

Huang, Yeu‐Shiang; Chen, Hung Wen

doi:10.1080/23302674.2016.1244302

Cited by 3 publications

(1 citation statement)

References 20 publications

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“…Consequently, it is necessary to determine appropriate dispatching and order release rules while considering fab process information in accordance with the changes in the environment. Other literature showed that closed-loop and global scheduling rules resulted in the procurement of better performance than other commonly used rules such as UNIF (Uniform), CONTIME (Constant time), FIFO (First in first out), EDD (Earliest due date), CR (Critical ratio), LPT (Longest processing time), and SPT (Shortest processing time) [21][22][23][24].…”

Section: T E Dmentioning

confidence: 99%

RETRACTED: The Optimal Decision Combination in Semiconductor Manufacturing

2017

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Wafer fabrication is a capital-intensive and highly complex manufacturing process. In a wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers in order to improve production efficiency and satisfy customers' demands of on-time delivery. Cycle time and average work-in-process reduction while meeting customers' requirements play an important role in improving the competitiveness and sustainability of a semiconductor manufacturer. In this research, we propose the optimal combination rules for lot scheduling problems in wafer fabs, focusing on three complex areas of decision making: lot release control, batch sizing, and dispatching lots to enhance competitiveness and sustainability of a semiconductor facility.

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Section: T E Dmentioning

confidence: 99%