A Micro Threading Based Concurrency Model for Parallel Computing

Abstract

The continuing launch of various multi-core processors backs parallel computing for gaining higher performance; however, it also exerts pressures on software developers concerning how to make full use of the multiplicity of resources to get the required benefits due to high coupling of parallel programs to specified hardware. In this paper, we propose SVP, a micro-threading based concurrency model, as an alternative to efficiently program on and manage multicore, even many-core systems. SVP isolates programming from executing resources so that programs are compiled once and execute regardless of actual cores available, not only numbers, but also properties to achieve scalable speedup. Such lower coupling, better flexibility and portability in parallel applications are highly appreciated. To investigate SVP, tool chains and a fully functional software simulator of an SVP many-core chip have been developed for test and verification. Using this infrastructure, we are able to show how much we can gain from SVP and how speedup is scaled by running the same binary code of Game of Life on a scalable many-core platform.

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches

“…Its success can be shown from the good scalability and flexibility over a range of benchmarks running on the Micro Grid [Bousias et al 2006;Bernard et al 2008;Yang et al 2011;]. However, It may be injected into another L2 cache with empty slot or matched tag, or retired to DRAM.…”