A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

Jagtap, Radhika; Kumar, Sumeet; Leuken, René van

doi:10.1109/dsd.2012.9

Cited by 11 publications

(5 citation statements)

References 14 publications

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“…Four geometries that form the limits of the TSV dimension range for 3D-SOC [16] are considered in order to derive the set of TSV parameters that result in the minimum and the maximum delay through the TSV. The TSV model trends observed by sweeping the material properties and the frequency indicated a large percentage change [17]. However, the impact of this change on the path delay is not significant once the overall path circuit is considered.…”

Section: Resultsmentioning

confidence: 99%

Balanced stochastic truncation of coupled 3D interconnect

Zjajo

Meijs

Leuken

2013

Proceedings of 2013 International Conference on IC Design &Amp; Technology (ICICDT)

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Abstract-Model order reduction techniques have been used extensively to reduce the complexity of extracted interconnect circuits and to expedite fast and accurate circuit simulation. In this paper, we introduce a balanced stochastic truncation in model order reduction of a coupled 3D interconnect to provide uniform approximation of the frequency response of the original system over the whole frequency domain. As the experimental results indicate, the proposed approach can significantly reduce the complexity of interconnect, while retaining high accuracy in comparison to the original model.

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Section: Resultsmentioning

confidence: 99%

Balanced stochastic truncation of coupled 3D interconnect

Zjajo

Meijs

Leuken

2013

Proceedings of 2013 International Conference on IC Design &Amp; Technology (ICICDT)

Self Cite

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“…4a. Table II shows all the values used in this study [24][25][26], noting that the length of the wires is assumed 200 µm similar to [17]. For the TSV technology, the experiments run once for C T SV =15 fF and another for C T SV =500 fF to cover the whole range of TSV capacitances and technologies, while the maximum value for R T SV =1 Ω is selected for all cases [17].…”

Section: A Technology Parasitics and Parametersmentioning

confidence: 99%

“…For the vertical interconnects, we choose the TSV capacitance to be a parameter in our simulations. The change in TSV capacitance reflects the change in TSV length and the resistivity of the substrate bulk used which in turn reflects different 3D integration technologies [17]- [20]. The data bus width N BW is assumed to be equivalent to the flit size, as shown in Figs.…”

Section: Introductionmentioning

confidence: 99%

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Said

Shalaby

Mehdipour

et al. 2016

Microprocessors and Microsystems

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Abstract-The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOXbased 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patterns.

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“…3d and 3e, respectively). According to [6], CT SV and RT SV can be assumed to be 15 fF and 1Ω, respectively. Wiring is assumed to be global.…”

Section: Design Considerations and Mod-elingmentioning

confidence: 99%

“…Wiring is assumed to be global. The length of the global wires is assumed 200 µm [6]. Global wiring parasitics are stated in Table 1 [7].…”

Section: Design Considerations and Mod-elingmentioning

confidence: 99%

A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias

Said

Mehdipour

Murakami

et al. 2015

Proceedings of the 3rd International Workshop on Many-Core Embedded Systems

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ABSTRACT3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. Though, there are still several challenges in 3D integration technology need to be addressed. It is shown in literature that reducing TSV count has a considerable effect in improving yield. The TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. The TSVBOX introduces some delay to the signals to be multiplexed. In this paper, we analyse the TSVBOX timing requirements and deduce a design methodology for TSVBOX-based 3D Network-on-Chip (NoC) to overcome the TSVBOX delay degradation. Performance comparisons under different traffic patterns are conducted to verify our solution. We show that TSVBOX-based 3D NoC performance is highly dependent on the NoC traffic pattern and in most simulation scenarios we tried, it shows almost the same performance of the conventional 3D NoC.

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A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

Cited by 11 publications

References 14 publications

Balanced stochastic truncation of coupled 3D interconnect

Balanced stochastic truncation of coupled 3D interconnect

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias

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