A method to speed up VLSI hierarchical physical design in floorplanning

Zhou, Yong‐Wu; Yan, Yunyao; Yan, Wei

doi:10.1109/asicon.2017.8252484

Cited by 8 publications

(2 citation statements)

References 7 publications

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“…Due to the increasing growth in the size and complexity of the VLSI design, it became challenging to achieve the speed and quality requirements of the IC design. As a result, in [10], an effective model for quick floor planning was presented in the VLSI topdown physical design flow that used active logic reduction technology to accelerate the design flow while reducing internal logic units and maintaining design quality. Logic optimization is the process of finding an equivalent representation of the logic circuit within predetermined constraints and is crucial to VLSI design.…”

Section: Related Workmentioning

confidence: 99%

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

Bukke,

Manjunathachari,

Sabbavarapu

2023

Eng. Technol. Appl. Sci. Res.

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In the modern era of signal processing, digital filters play an important role in real-time applications such as communication, consumer electronics, digital signal processing, audio, etc. In digital filter design, Finite Impulse Response (FIR) filters are highly preferable due to their linear phase and inherent stability. These filters benefit from being time-invariant and simple to implement with minimal computational requirements. Therefore, the hardware security of FIR filters is essential for good performance and reliable results. On the other hand, there is the possibility of hardware threats, such as tampering, reverse engineering, hardware Trojans, etc., as the design of an FIR filter involves many stages. Such hardware attacks on FIR filters can cause several problems, including performance degradation, leakage of confidential information, lack of stability, etc. This study presents the design and implementation of a Trojan-aware FIR filter using Physical Unclonable Functions (PUFs). The key feature of PUFs is that they generate a unique and unpredictable response for each given challenge. In the proposed design, PUFs were used to generate the FIR filter coefficients that are unique and unpredictable by attackers/trojans to improve security. The security of FIR with PUF was tested using ML-based challenges, and the results showed approximately 30% more reliability and consistency compared to the FIR without PUFs.

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Section: Related Workmentioning

confidence: 99%

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

Bukke,

Manjunathachari,

Sabbavarapu

2023

Eng. Technol. Appl. Sci. Res.

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“…Even though by using this algorithms and methods taking more amount of time and doing more iterations. Using a method of Flex model-based method reduces unnecessary instances which improves run time and CPU in chip planning stage [1]. However, it is also taking more iterations.…”

Section: Introductionmentioning

confidence: 99%

BlackBox Model Based VLSI Hierarchical Floorplanning

Kallam*¹,

Gundala²

2019

IJEAT

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Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of Backbox model based top level hierarchical floorplanning based physical design. The main aim of this project is to reduce the number of instances which are not necessary in the top level chip floor planning which reduces peak memory for the design and also reducing CPU run time for getting proper prototype design in the top level ASIC design and estimate the congestion in the design at initial stage and modify floor planning to obtain quality of prototype model in the floorplanning. This project is designed on cadence encounter tool.

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