A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Fan, Heng; Jiang, Lingli; Zhang, Bo

doi:10.1109/tdmr.2012.2210043

Cited by 12 publications

(3 citation statements)

References 11 publications

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“…[2] The methods to improve the V h of SCRs have motivated many research teams. [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] One method is the segmented technique, which was proposed in Refs. [3] and [14] to reduce the emitter injection efficiency.…”

Section: Introductionmentioning

confidence: 99%

High holding voltage SCR for robust electrostatic discharge protection

Zhao

Qiao

et al. 2017

Chinese Phys. B

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A novel silicon controlled rectifier (SCR) with high holding voltage (V h ) for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high V h by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (I ESD ), the two SCRs are turned on at the same time to induce the first snapback with high V h (V h1 ). As the I ESD increases, the SCR2 will be turned off because of its low current gain. Therefore, the I ESD will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V h (V h2 ). The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized V h2 of 7.4 V with a maximum failure current (I t2 ) of 14.7 mA/µm is obtained by the simulation.

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Section: Introductionmentioning

confidence: 99%

High holding voltage SCR for robust electrostatic discharge protection

Zhao

Qiao

et al. 2017

Chinese Phys. B

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“…[1][2][3][4] To achieve a high breakdown voltage, the power device structure is implemented as an ESD device. [5] The conventional laterally diffused metal-oxide semiconductor (LDMOS) used as an output driver is always vulnerable to ESD. [6,7] An effective method to solve this problem is to use a semiconductor control rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS); [8] however, its low holding voltage and latch-up immunity are challenging issues for its application.…”

Section: Introductionmentioning

confidence: 99%

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

Ma¹,

Qiao²,

Zhang³

2015

Chinese Phys. B

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A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-µm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

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“…As the trend to more advanced semiconductor manufacturing process continues, sufficient electrostatic discharge (ESD)/ latch-up (LU) capabilities have become very important [1][2]. The ESD/LU impacts on an IC reliability discloses the extremely serious consequence, which can cause the yield of many electronic products low, but also results in huge money losses.…”

Section: Introductionmentioning

confidence: 99%

The Source Pick-Up Effect of Multi-Finger GDpMOSTs on ESD/LU Immunities in a 3.3V 0.35μm Process

Chen

Lee

2013

AMM

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This paper presents an evaluation of source N+ pick-up influence on ESD/LU immunities for the 0.35μm 3.3V low-voltage pMOSFET devices. It is found that when the stripe number of source N+ pick-up increased, the trigger voltage (Vt1) and holding voltage (Vh) values will be increased, too. Finally, the It2 value of DUTPick-up×5 as compared with a DUTWo pick-up(reference group) is decreased by 10%. Therefore, it can be concluded that the contribution of source N+ pick-up for It2 was not remarkable and recommended in this 0.35μm 3.3V process. Additionally, the Vh value of DUTPick-up×5 as compared with a DUTWo pick-up(reference group) is increased by 9.4%, the source N+ pick-up process can effectively strengthen the latch-up immunity.

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A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Cited by 12 publications

References 11 publications

High holding voltage SCR for robust electrostatic discharge protection

High holding voltage SCR for robust electrostatic discharge protection

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

The Source Pick-Up Effect of Multi-Finger GDpMOSTs on ESD/LU Immunities in a 3.3V 0.35μm Process

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