High holding voltage SCR for robust electrostatic discharge protection

Abstract

A novel silicon controlled rectifier (SCR) with high holding voltage (V h ) for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high V h by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (I ESD ), the two SCRs are turned on at the same time to induce the first snapback with high V h (V h1 ). As the I ESD increases, the SCR2 will be turned off because of its low current gain. Therefore, the I ESD will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V h (V h2 ). The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized V h2 of 7.4 V with a maximum failure current (I t2 ) of 14.7 mA/µm is obtained by the simulation.

A modified low voltage triggered silicon controlled rectifier (SCR) for ESD applications

“…The segmentation technique was introduced to reduce the emitter injection efficiency of the parasitic NPN and PNP transistors, thereby increasing the holding voltage of SCR. However, the segmentation technique will cause non-uniform conduction of current inside the SCR device [1][2][3], which was also introduced in this article to implement the proposed MLVTSCR. By segmenting the N + active area bridged on the PW/NW junction of LVTSCR into blocks by P + region, MLSCR was integrated into LVTSCR, thus the I-V curve in figure 8 shows a multi-trigger phenomenon.…”

“…However, the high trigger voltage of the SCR may not protect the gate oxide properly. To optimize the trigger voltage of the SCR and provide more efficient on-chip ESD protection, modified lateral SCR (MLSCR) and low-voltage triggered SCR (LVTSCR) have been proposed [2,3]. LVTSCR improves the trigger voltage by introducing a GGNMOS into SCR, but the strong snapback of SCR leads to a low holding voltage, result in risks of latch-up [4].…”

New DDSCR structure with high holding voltage for robust ESD applications*

“…Silicon controlled rectifier (SCR) is popularly used due to its efficient release capacity per unit area, but the working mechanism of SCR under negative pulse is of diode. [1][2][3] In the control bus, the signal from the A/B port is bidirectional, the ESD protection should be considered to be also bidirectional, the DDSCR is selected, and the DDSCR device can optimize the ESD characteristics of the DDSCR by changing the structure and size. The deep snapback phenomenon of DDSCR will also cause some problems with high trigger voltage and low holding voltage.…”

Design of a novel high holding voltage LVTSCR with embedded clamping diode*

“…Various researches have been carried out based on the conventional ESD protection structures such as diode, metal-oxide-semiconductor (MOS) and silicon controlled rectifier (SCR). [2][3][4][5][6][7][8][9] The diode [2] and gate-grounded NMOS (GGNMOS) [3] are attractive because of their small snapback margin. However, they have poor ESD robustness [4] and need large chip area to reach the required ESD protection level, [5] resulting in the increasing cost.…”

“…However, they have poor ESD robustness [4] and need large chip area to reach the required ESD protection level, [5] resulting in the increasing cost. The SCR is usually regarded as a promising ESD protection device due to its strong ESD robustness per unit area [6] and small parasitic effect, [7] whereas it is restrained from wide applications due to the high trigger voltage (V t1 ) [8] and low holding voltage (V h ), [9] which may result in the breakdown or latch-up of protected circuits.…”