A Method for the Simultaneous Suppression of DC Capacitor Fluctuations and Common-Mode Voltage in a Five-Level NPC/H Bridge Inverter

Abstract

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.

Research and Modeling of Photovoltaic Array Channel Noise Characteristics

“…For photovoltaic power plants without isolation transformers, no batteries, and no EMI filters in the DC-side, the inverters will generate severe common-mode and differential-mode interference among photovoltaic arrays channel when they are connected to the grid [11][12][13][14]. Therefore, it is necessary to grasp the channel noise characteristics of the photovoltaic array, laying a foundation for ensuring the progress of carrier communication among photovoltaic arrays.…”