A Method Based on Petri Nets and a Matrix Model to Implement Reconfigurable Logic Controllers

Silva, C F; Quintans, C.; Colmenar, A.; Castro, Manuel; Mandado, Enrique

doi:10.1109/tie.2009.2038946

Cited by 10 publications

(4 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The idea is mainly oriented for reconfigurable FPGA devices which are currently an interesting and on-time research topic (Petri nets and FPGAs are also considered in [32]). Informal specification is formalized by means of interpreted Petri nets.…”

Section: Discussionmentioning

confidence: 99%

Decomposition, validation and documentation of control process specification in form of a Petri net

Grobelna

Wiśniewska

Wiśniewski

et al. 2014

2014 7th International Conference on Human System Interactions (HSI)

View full text Add to dashboard Cite

The article focuses on some aspects regarding logic controller design. Control process is formally specified using interpreted Petri nets. It is then formally verified against behavioral properties using model checking technique and temporal logic. Formal specification can also be documented as UML activity diagram. One can then benefit from advantages of both specification techniques -Petri nets with a wide range of mathematical support and user-friendly UML activity diagrams. An interpreted Petri net can also be decomposed into state machine components (SMCs), each of them to be implemented in a separate module of FPGA device.

show abstract

Section: Discussionmentioning

confidence: 99%

Decomposition, validation and documentation of control process specification in form of a Petri net

Grobelna

Wiśniewska

Wiśniewski

et al. 2014

2014 7th International Conference on Human System Interactions (HSI)

View full text Add to dashboard Cite

show abstract

“…Several other methodologies to translate PN models in VHDL have been developed [Silva et al (2010)] [Tkacz and Adamski (2012)]. The advantage of the HILECOP one is that it handles generalized T-time PN whereas other methodologies deal with binary non-time PN.…”

Section: Integrating Implementation Properties In Analysis Of Petri Nmentioning

confidence: 99%

Integrating implementation properties in analysis of Petri nets handling exceptions

Leroux

Godary-Dejean

Andreu

2014

IFAC Proceedings Volumes

View full text Add to dashboard Cite

To design and implement complex digital systems, designers need to have an efficient methodology. In this goal, HILECOP has been developed to transform automatically Petri nets in a VHDL code. To ease design and increase the reactivity of exception handling, the mechanism of macroplace has been added to the formalism of Petri nets. This article describes an automatic model transformation for the analysis step. It integrates implementation properties to enhance reliability.

show abstract

“…Several other methodologies to translate PN models in VHDL have been developed [10][11] [12]. In all these methodologies the execution of the Petri nets is implemented synchronously but they all deal only with binary non-time PN.…”

Section: Introductionmentioning

confidence: 99%

“…In all these methodologies the execution of the Petri nets is implemented synchronously but they all deal only with binary non-time PN. In [10] [11], they set the hypothesis that there is no conflict in the model. In [12], conflicts are handled thanks to inhibitor or enabling arcs, hence it is the designer responsibility to deal with conflicts.…”

Section: Introductionmentioning

confidence: 99%

Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation

Leroux¹,

Godary-Dejean²,

Coppey

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

View full text Add to dashboard Cite

Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution for binary Petri nets is proposed. For the generalized case, two solutions are proposed and experimentally compared. Thus a solution is provided for the implementation of interpreted generalized time Petri nets.

show abstract

A Method Based on Petri Nets and a Matrix Model to Implement Reconfigurable Logic Controllers

Cited by 10 publications

References 31 publications

Decomposition, validation and documentation of control process specification in form of a Petri net

Decomposition, validation and documentation of control process specification in form of a Petri net

Integrating implementation properties in analysis of Petri nets handling exceptions

Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation

Contact Info

Product

Resources

About