A Metastability-Free Multi-synchronous Communication Scheme for SoCs

Polzer, Thomas; Handl, Thomas; Steininger, Andreas

doi:10.1007/978-3-642-05118-0_40

Cited by 8 publications

(13 citation statements)

References 13 publications

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“…Type (ii) clocking schemes are particularly beneficial from a designer's point of view, since they combine the convenient local synchrony of a GALS system with a global time base across the whole chip. It has been shown in [27] that these properties indeed facilitate metastability-free high-speed communication across clock domains.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation

Dolev

Függer

Lenzen

et al. 2011

Lecture Notes in Computer Science

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Today's hardware technology presents a new challenge in designing robust systems. Deep submicron VLSI technology introduced transient and permanent faults that were never considered in low-level system designs in the past. Still, robustness of that part of the system is crucial and needs to be guaranteed for any successful product. Distributed systems, on the other hand, have been dealing with similar issues for decades. However, neither the basic abstractions nor the complexity of contemporary fault-tolerant distributed algorithms match the peculiarities of hardware implementations.This paper is intended to be part of an attempt striving to overcome this gap between theory and practice for the clock synchronization problem. Solving this task sufficiently well will allow to build a very robust high-precision clocking system for hardware designs like systems-on-chips in critical applications. As our first building block, we describe and prove correct a novel Byzantine fault-tolerant self-stabilizing pulse synchronization protocol, which can be implemented using standard asynchronous digital logic. Despite the strict limitations introduced by hardware designs, it offers optimal resilience and smaller complexity than all existing protocols.

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Section: Introduction and Related Workmentioning

confidence: 99%

Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation

Dolev

Függer

Lenzen

et al. 2011

Lecture Notes in Computer Science

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show abstract

“…On this foundation it is straightforward to build a fault-tolerant architecture on the level of functional modules. Furthermore, the global synchrony allows metastability-free communication between the functional units without the need for synchronizers [32]. Another advantage of our approach is its insensitivity to delays in the communication links as well as to the TG-Alg's propagation delays; as we will show later, even considerable tolerances, drift and jitter, can be accommodated.…”

Section: The Darts Conceptmentioning

confidence: 96%

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Fuchs

Steininger

2011

Journal of Electrical and Computer Engineering

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We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply-properties that are considered highly desirable for future technology nodes.

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“…It has been shown by Polzer et al [2009] that these properties indeed facilitate metastability-free high-speed communication across clock domains.…”

Section: Problem Motivationmentioning

confidence: 97%

Fault-tolerant algorithms for tick-generation in asynchronous logic

Dolev

Függer

Schmid

et al. 2014

J. ACM

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Today's hardware technology presents a new challenge in designing robust systems. Deep submicron VLSI technology introduces transient and permanent faults that were never considered in low-level system designs in the past. Still, robustness of that part of the system is crucial and needs to be guaranteed for any successful product. Distributed systems, on the other hand, have been dealing with similar issues for decades. However, neither the basic abstractions nor the complexity of contemporary fault-tolerant distributed algorithms match the peculiarities of hardware implementations.This article is intended to be part of an attempt striving to bridge over this gap between theory and practice for the clock synchronization problem. Solving this task sufficiently well will allow to build an ultrarobust high-precision clocking system for hardware designs like systems-on-chips in critical applications. As our first building block, we describe and prove correct a novel distributed, Byzantine fault-tolerant, probabilistically self-stabilizing pulse synchronization protocol, called FATAL, that can be implemented using standard asynchronous digital logic: Correct FATAL nodes are guaranteed to generate pulses (i.e., unnumbered clock ticks) in a synchronized way, despite a certain fraction of nodes being faulty. FATAL uses randomization only during stabilization and, despite the strict limitations introduced by hardware designs, offers optimal resilience and smaller complexity than all existing protocols. Finally, we show how to leverage FATAL to efficiently generate synchronized, self-stabilizing, high-frequency clocks. ACM Reference Format:Dolev, D., Függer, M., Schmid, U., and Lenzen, C. 2014. Fault-tolerant algorithms for tick-Generation in asynchronous logic: Robust pulse generation.

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A Metastability-Free Multi-synchronous Communication Scheme for SoCs

Cited by 8 publications

References 13 publications

Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation

Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Fault-tolerant algorithms for tick-generation in asynchronous logic

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