A mesh-arrayed MOSFET (MA-MOS) for high-frequency analog applications

Shimomura,; Matsuzawa,; Kimura,; Hayashi, Tetsuya; Hirai,; Kanda,

doi:10.1109/vlsit.1997.623701

Cited by 13 publications

(4 citation statements)

References 4 publications

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“…Moreover, while the cut-off frequency can be increased by gate length downscaling, the performance factors such as maximum oscillation frequency and minimum noise figure depend strongly on the parasitic components [82][83][84].…”

Section: Minimum Noise Figurementioning

confidence: 99%

Review on analog/radio frequency performance of advanced silicon MOSFETs

Passi

Raskin

2017

Semicond. Sci. Technol.

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Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of draininduced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore's law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.Keywords: analog and radio-frequency figures of merit, digital figures of merit, multiple gate field effect transistor, ultra-thin body buried-oxide, III-V and two-dimensional channel field effect transistor

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Section: Minimum Noise Figurementioning

confidence: 99%

Review on analog/radio frequency performance of advanced silicon MOSFETs

Passi

Raskin

2017

Semicond. Sci. Technol.

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“…However, both the better g m and poorer R g dominate the NF min as scaling to 65-nm-node devices. The larger R g is unavoidable in highly scaled transistors, which also causes the degradation of f max even under the higher f T and lower C gd during scaling: 17) V g (V) Frequency (GHz)…”

Section: Resultsmentioning

confidence: 99%

Radio Frequency Performance Improvement with Drain Bias and Limiting Factors of 65-nm-Node Radio Frequency Metal–Oxide–Semiconductor Field-Effect Transistors

Kao¹,

Lu²,

Chang³

2009

jjap

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With the continuous down scaling of radio frequency metal-oxide-semiconductor field-effect transistors (RF MOSFETs) into a 65 nm node, the RF performance of unity-gain cutoff frequency ( f T ), the maximum frequency of oscillation ( f max ), and the minimum noise figure (NF min ) show much smaller dependences on short-channel effects due to increases in drain current and transconductance (g m ), which originate from the short-channel effects. We have studied the effect of drain bias on the RF performance of 65-nm-node MOSFETs. Both the f T and NF min improve linearly with increasing drain voltage, in contrast with their independence on drain bias in longer-channel devices. Additionally, although f T improves continuously in sub-65-nm node devices, f max and NF min deteriorate more in 65-nm-node transistors than in 90-nm-node devices owing to a limiting parasitic effect.

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“…The gate resistance can be reduced drastically with increase of division number, since the gate resistance is inversely proportional to the square of division numbers. A meshed array structure shown in figure 8 is an interesting layout to reduce the gate resistance and drain capacitance [10]. Figure 7 shows the sheet resistance versus gate length for some gate materials.…”

Section: Maximum Oscillation Frequency: Fmaxmentioning

confidence: 99%