A memory-based high-speed digital delay line with a large adjustable length

Mattausch, H. J.; Matthiesen, F.; Hartl, J.; Tielert, R.; Jacobs, E.P.

doi:10.1109/4.265

Cited by 10 publications

(2 citation statements)

References 2 publications

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“…Note that three such copies of the filter are required to compute all three interpolated output pixels in parallel. The computation and control parts required an area of 35.3 mm at m. The delay lines required an estimated area (based on [11]) of mm at m. This implies a total area of mm at m. Assuming that the areas scale by…”

Section: F System Discussion and Vlsi Designmentioning

confidence: 99%

Algorithm and VLSI architecture for high performance adaptive video scaling

Raghupathy

Chandrachoodan

Liu

2003

IEEE Trans. Multimedia

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We propose an efficient high-performance scaling algorithm based on the oriented polynomial image model. We develop a simple classification scheme that classifies the region around a pixel as an oriented or nonoriented block. Based on this classification, a nonlinear oriented interpolation is performed to obtain high quality video scaling. In addition, we also propose a generalization that can perform scaling for arbitrary scaling factors. Based on this algorithm, we develop an efficient architecture for image scaling. Specifically, we consider an architecture for scaling a Quarter Common Intermediate Format (QCIF) image to 4CIF format. We show the feasibility of the architecture by describing the various computation units in a hardware description language (Verilog) and synthesizing the design into a netlist of gates. The synthesis results show that an application specific integrated circuit (ASIC) design which meets the throughput requirements can be built with a reasonable silicon area.Index Terms-Adaptive scaling, oriented polynomial interpolation, video zoom, VLSI architecture.

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Section: F System Discussion and Vlsi Designmentioning

confidence: 99%

Algorithm and VLSI architecture for high performance adaptive video scaling

Raghupathy

Chandrachoodan

Liu

2003

IEEE Trans. Multimedia

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“…Commonly used delay circuits based on simple shift registers called Variable Register Delay (VRD) [1 ], memory or FIFO [2], and CCD [3] approach have the inherent property that only the numerator control word P is programmable while Q = K = 1.…”

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confidence: 99%

A Widely Programmable Multiply/Divide Digital Delay Line

Dam

Saha

1990

IETE Technical Review

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A ne"· programmable Multiply/Divide Digital Delay Line drcuit is proposed and CIF obtained for the layout design of the delay line chip "'ith 3p, CMOS standard cells. The chip is designed to control the delay or a 4 bit data word 1tith 4 bit wide multiply programme "'ord P and 8 bit llidc devide programme word Q. The circuit is suited to low frequency operation and large delay generation. With a basic crystal frequency of 4 MHz, the circuit can be programmed to produce delays ranging from 0.06425 milli second to 139.264 milli second. Such a delay line chip may find wide application in factory automation, office automation and process industries. The complexity Clf the delay line chip is equivalent to 1348 two input NAND gates. After final placement and routing the chip size is 6782p, • 5898p, and estimated power di~ipation is 9. 7607 m W for a 5 volt po\nr supply.

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