A Widely Programmable Multiply/Divide Digital Delay Line

Abstract

A ne"· programmable Multiply/Divide Digital Delay Line drcuit is proposed and CIF obtained for the layout design of the delay line chip "'ith 3p, CMOS standard cells. The chip is designed to control the delay or a 4 bit data word 1tith 4 bit wide multiply programme "'ord P and 8 bit llidc devide programme word Q. The circuit is suited to low frequency operation and large delay generation. With a basic crystal frequency of 4 MHz, the circuit can be programmed to produce delays ranging from 0.06425 milli second to 139.264 milli second. Such a delay line chip may find wide application in factory automation, office automation and process industries. The complexity Clf the delay line chip is equivalent to 1348 two input NAND gates. After final placement and routing the chip size is 6782p, • 5898p, and estimated power di~ipation is 9. 7607 m W for a 5 volt po\nr supply.