A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard

Palomino, Daniel; Sampaio, Felipe; Agostini, Luciano; Bampi, Sérgio; Susin, Altamiro

doi:10.1109/icip.2012.6466830

Cited by 34 publications

(17 citation statements)

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“…Architecture described in [2] and [3] provides the greatest throughputs, but severely limits the compression efficiency by employing only 4x4 PU sizes. On the other hand, designs presented in [6] and [8] supports all prediction parameters with lower throughputs. The highest throughput is achieved in [5].…”

Section: Resultsmentioning

confidence: 89%

“…However, this work actually focuses on optimizations and transformations of Angular prediction equations. The more recent works [5], [6] support removed 64x64 PU size. The impressive throughput of [5] involves considerable resource consumption, while the architecture described in [6] is unable to encode HDTV sequences in real-time.…”

Section: Introductionmentioning

confidence: 96%

“…The more recent works [5], [6] support removed 64x64 PU size. The impressive throughput of [5] involves considerable resource consumption, while the architecture described in [6] is unable to encode HDTV sequences in real-time. An interesting approach is presented in [7], where the set of possible intra prediction parameters is initially constrained thanks to the analysis of the original samples.…”

Section: Introductionmentioning

confidence: 96%

See 2 more Smart Citations

A double-path intra prediction architecture for the hardware H.265/HEVC encoder

Abramowski

Pastuszak

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4x4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separate reconstruction loop. The final result from this path is then incorporated into the second path, independently checking all the remaining PUs. This approach does not entail a significant increase in utilization of hardware resources, while considerably accelerates the encoding. The proposed architecture can operate at 100 MHz for FPGA Aria II devices and at 200 MHz for the TSMC 0.13µm technology. The achieved throughput allows the processing of almost 17.5 and 35 1080p frames per second using FPGA and ASIC technology, respectively. The solution is compliant with the Main, Main 10, and Main Still Picture profiles of the H.265/HEVC standard.

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Section: Resultsmentioning

confidence: 89%

Section: Introductionmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 96%

See 1 more Smart Citation

A double-path intra prediction architecture for the hardware H.265/HEVC encoder

Abramowski

Pastuszak

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…For hardware implementation of intra prediction, an architecture for intra 4 4 prediction with flexible reference sample selection is proposed in [28]. A full intra architecture is also proposed in [33]. In high throughput applications, intra prediction performance still needs to be improved.…”

Section: Intra Predictionmentioning

confidence: 99%

Encoder Hardware Architecture for HEVC

Tsai

Chen

2014

Integrated Circuits and Systems

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In this chapter, an encoder hardware architecture design for HEVC is described. The system pipeline is first introduced followed by the design details of the different HEVC encoder modules such as inter prediction, intra prediction, mode decision, in-loop filters, and entropy coding. Finally, a sample test chip implementation result is presented as a reference. IntroductionHigh density large-sized displays that provide an immersive display experience are being widely adopted in multimedia application terminals. The next generation display panels are expected to be 4K/8K (Ultra High Definition Television (UHDTV) resolution) or even higher. As a result, the video resolution required is also becoming higher. To reduce the storage and transmission requirements of largesized video, HEVC video encoding, that provides around 50 % better compression efficiency than H.264/AVC, is recommended. However, real-time high resolution video encoding in HEVC requires hardware support due to the complexity.The HEVC Test Model (HM) is the reference software for HEVC developed during standardization of HEVC. The HM encoder was designed to maximize the coding gain achievable by HEVC. Real-time performance was not a major objective. The HM encoder can be used for a wide variety of applications including offline encoding [30]. However, the encoding methods in HM do not necessarily map to the most efficient design for a real-time hardware encoder. Hardware consideration is quite different from software and is very challenging. For H.264/AVC, many stateof-the-art H.264/AVC encoder architectures [4,5,18,23,43] have been presented.

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“…There are a few HEVC intra prediction hardware implementations in the literature [16], [17]. Since these hardware only implement HEVC intra prediction, the HEVC intra mode decision hardware proposed in this paper cannot be compared with them.…”

Section: Fig 1 Addition Amounts In Hevc and H264 Satd Calculationsmentioning

confidence: 99%