A double-path intra prediction architecture for the hardware H.265/HEVC encoder

Abstract

This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4x4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separate reconstruction loop. The final result from this path is then incorporated into the second path, independently checking all the remaining PUs. This approach does not entail a significant increase in utilization of hardware resources, while considerably accelerates the encoding. The proposed architecture can operate at 100 MHz for FPGA Aria II devices and at 200 MHz for the TSMC 0.13µm technology. The achieved throughput allows the processing of almost 17.5 and 35 1080p frames per second using FPGA and ASIC technology, respectively. The solution is compliant with the Main, Main 10, and Main Still Picture profiles of the H.265/HEVC standard.

Hardware Architecture for Realtime HEVC Intra Prediction

“…The memory utilization of our design is high because all reconstructed samples are stored in register buffers, including the original buffer, reference buffer, and control buffer, as shown in Figure 5. Compared to earlier works, the proposed design [13] accelerates the throughput of the most frequently used PU (PU 4 × 4). This approach provides a frame rate of 4.38 FPS for the 4K resolution.…”

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder

“…Kalali et al [11] introduced a low energy architecture with computation reduction techniques. To reduce the computational complexity of 4 × 4 PU, Abramowski et al [12] created a separate path to process the 4 × 4 PU prediction with little increase of hardware consummation, which is also adopted in [13]. Liu et al [14] proposed a reconfigurable intra prediction architecture to avoid the transpose register array which can support 2560 × 1600 video coding.…”