A MAGFET sensor array for digital magnetic signal reading

Rohrer, S.; Hentschke, S.; Reifschneider, N.

doi:10.1109/asic.1997.617027

Cited by 5 publications

(1 citation statement)

References 3 publications

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“…D UE TO FULL CMOS process-compatibility and good magnetic linearity, the magnetic field-effect transistor (MAGFET) is often combined together with other integrated electronic circuits to detect the strength of the applied magnetic field [1], to realize a magneto-electric function [2], or to recognize a magnetic field pattern [3], [4]. Unfortunately, its magnetic resolution is limited by the intrinsically low magnetic sensitivity, and the bit error rate (BER) is high for weak digital magnetic field detection.…”

Section: Introductionmentioning

confidence: 99%

Weak magnetic field pattern detection by CMOS magnetic latch

Sun

2003

IEEE Electron Device Lett.

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A CMOS magnetic latch for digital magnetic field detection is reported. It is based on a single split-drain magnetic field-effect transistor with a positive feedback imported by a pair of lateral floating gates. The magnetic latch achieves its maximum magnetic sensitivity when latch-up takes place. A linear equation is used to model the positive feedback and the latch-up process. By imposing a reset-evaluation mechanism, the magnetic latch is evaluated for digital magnetic pattern detection. Experimental results show that the minimum detectable magnetic flux density for the magnetic latch could be down to less than 0.1 mT with low bit error rate.Index Terms-CMOS magnetic latch, magnetic field-effect transistor (MAGFET), magnetic field measurement, magnetic pattern recognition.

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Section: Introductionmentioning

confidence: 99%