A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic

Hu, Jianping; Xu, Tao; Li, Hong

doi:10.1093/ietisy/e88-d.7.1479

Cited by 61 publications

(13 citation statements)

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“…Node Capacitance and switching activities. The conventional low power techniques have several challenges with the shrink of CMOS technology sizes, degraded voltage gain, increased speed, increased leakage current and soft error rates [23].the past few years several effective power management design technique have been developed including lowering the supply voltage, low threshold voltage and gating off the clock signal when not in use and designing low power switching functionality of logic gate circuits. These techniques very widely using in industry [24].The multiplexer gate has the largest power consumption because of its complicated XMOS structure and the presence of additional input in GDI cell technique.…”

Section: Reversible Logic For Low Power Designmentioning

confidence: 99%

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Sharma¹,

Singh²,

Akashe³

2013

IJCA

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Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

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Section: Reversible Logic For Low Power Designmentioning

confidence: 99%

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Sharma¹,

Singh²,

Akashe³

2013

IJCA

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“…In recent years, several adiabatic logic families have been proposed for low power systems [2][3][4][5]. Some adiabatic logic circuits, such as the efficient charge recovery logic (ECRL) [6] and the pass-transistor adiabatic logic circuits with NMOS pull-down configuration (PAL-2N) [7] etc, are applied for memories, and they are used to drive address lines, bit lines, and word lines.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits

2009

2009 Pacific-Asia Conference on Circuits, Communications and Systems

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A 32×32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18μm process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the adiabatic register file can work very well.

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“…Compared with the conventional low-power approaches, power dissipation can be significantly reduced by using the adiabatic computation [2][3][4][5][6][7]. Adiabatic logic circuits utilize AC voltage supplies (power-clocks) to recycle the energy of circuit nodes.…”

Section: Introductionmentioning

confidence: 99%

“…This approach overcomes the C L V 2 DD barrier faced by the conventional CMOS logic, thus their energy dissipations are much smaller than that of the conventional CMOS circuits. Several adiabatic logic architectures, such as positive feedback adiabatic logic (PFAL) [3,4], complementary pass-transistor adiabatic logic (CPAL) [5], efficient charge recovery logic (ECRL) [6], etc., have been reported and achieved considerable energy savings.…”

Section: Introductionmentioning

confidence: 99%

Low-power interface circuits between adiabatic and standard CMOS circuits

Zhou

Wang

et al. 2008

Analog Integr Circ Sig Process

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The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 lm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.

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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic

Cited by 61 publications

References 0 publications

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits

Low-power interface circuits between adiabatic and standard CMOS circuits

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