A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

Juang, Tso-Bing; Chen, Sheng-Hung; Cheng, Huang-Jia

doi:10.1109/tcsii.2009.2035270

Cited by 62 publications

(6 citation statements)

References 18 publications

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“…Correction strategies used for 2, 6, and 7 regions with changing hardware complexity and accuracy [12]. In 2004, a 2-region error manipulation schemes were proposed by Juang et al [15,16] and advancement of this work is introduced for logarithmic and antilogarithmic converter. Juang et al [16] have proposed 2-region correction by using bit level manipulation schemes to achieve trade-off.…”

Section: Literature Reviewmentioning

confidence: 99%

An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

Nandan¹,

Mahajan²,

Kanungo³

2021

MMEP

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An applications of signal processing are frequently used everywhere in day-to-day life. “Digital Signal Processing (DSP)” has been basic requirement of efficient and accurate arithmetic operations for performing fast and accurate signal processing. Logarithm arithmetic provides an option of that desire. In this work, it is presented an efficient VLSI implementation of an antilogarithm converter by using 10-region error correction. It provides error efficient implementation with significant hardware gain. VLSI implementation of reported and proposed antilogarithmic converters design created in Xilinx ISE 12.1. Antilogarithmic converters (reported and proposed design) are synthesized by using Synopsys design software perform the RTL Synthesis analysis by using package design compiler. This paper presents 10- region converter which considers design trade-off where proposed demonstrates 19.75%, 31.02%, 12.65%, 44.65% and 29.91% respective reduction in comparison of previous design. Error analysis was done using MATLAB for proposed conversion method and reported methods. Suggested antilogarithmic converters have 1.559% error only in comparison of 1.7327% error reported by Kuo et al. On behalf of hardware complexity and error analysis results, it can say that the proposed converters could perform better in comparisons of all aspects of reported design.

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Section: Literature Reviewmentioning

confidence: 99%

An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

Nandan¹,

Mahajan²,

Kanungo³

2021

MMEP

View full text Add to dashboard Cite

show abstract

“…It can reduce the approximation errors, but suffers from hardware overhead due to many regions of approximation [28]. A similar approach of 2-region bit-level manipulation has been used to achieve accuracy for an antilogarithmic converter [21,22]. Kuo et al have proposed 4region shift-and-add approximations based antilogarithmic converter in 2012.…”

Section: Systematic Growth Of Literaturementioning

confidence: 99%

“…The pictorial representation of logarithm multiplication is shown in Figure 1. Many methods regarding binary to logarithmic conversion and vice versa have been discussed in the last few years [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. Error creates at the time of logarithmic and antilogarithmic conversion [10].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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“…These require circuits for complex arithmetic computations such as multiplication, division, square root, squaring, and powering, which entail additional hardware costs and longer latency. To reduce the hardware costs and transmission delays, recent studies have developed novel methods to replace the complex arithmetic computations, such as the CORDIC algorithm [1], the table-based algorithm using rectangular multipliers [2], and the logarithmic number system (LNS) [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] to handle arithmetic computations. The CORDIC algorithm [1] uses an iterative method, and is not suitable for three-dimensional real-time DSP because of the limitation of operation speed.…”

Section: Introductionmentioning

confidence: 99%

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Kuo

2024

Applied Sciences

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Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

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A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

Cited by 62 publications

References 18 publications

An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

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